 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ICs for Communications S/T Bus Interface Circuit Extended SBCX PEB 2081 Version 3.4 User's Manual 11.96 T2081-XV34-M2-7600 Edition 11.96 This edition was realized using the software system FrameMaker. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu- ICs for Communications S/T Bus Interface Circuit Extended SBCX PEB 2081 Version 3.4 User's Manual 11.96 PEB 2081 Revision History: Previous Version: Page Page (in previous (in new Version) Version) Current Version: 11.96 Subjects (major changes since last revision) General Information Contents Page Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 1.1 1.2 1.3 1.4 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 3 3.1 3.2 3.2.1 3.2.1.1 3.2.1.1.1 3.2.1.1.2 3.2.1.2 3.2.1.3 3.2.1.3.1 3.2.1.3.2 3.2.1.3.3 3.2.1.3.4 3.2.1.3.5 3.2.1.3.6 3.2.1.3.7 3.2.1.3.8 3.2.1.3.9 3.2.1.4 3.2.2 3.2.3 3.2.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 13 14 15 System Integration and Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operational Modes and System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TE Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ISDN Network Termination (NT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ISDN Network Terminator (NT1) in Star Configuration . . . . . . . . . . . . . . . . . . . . . . . 20 ISDN Network Terminator Using IOM(R)-2 Architecture (Intelligent NT) . . . . . . . . . . . 24 Line Card Application (one D-channel controller per line) . . . . . . . . . . . . . . . . . . . . . 27 Line Card Application (one D-channel controller for eight lines) . . . . . . . . . . . . . . . . 29 Private-Branch-Exchange Application (one D-channel controller per line) . . . . . . . . 31 Setting Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 S/T-Interface Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Application Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SBCX Device Architecture and General Functions . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Frame Structure/Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface Line Card Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface Terminal Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface Command / Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Procedure "Timeout" (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MON-1, MON-2 Commands (S/Q Channel Access) . . . . . . . . . . . . . . . . . . . . . . . . . MON-8 Commands (Internal Register Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MON-8 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MON-8 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MON-8 Loop-Back Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MON-8 IOM(R)-2 Channel Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MON-8 SM/CI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAI Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Auxiliary Interface (MAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Specific Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 43 45 45 45 47 48 50 54 54 58 58 60 61 61 62 63 64 64 65 66 66 Semiconductor Group 3 General Information Contents (cont'd) 3.2.3.2 3.2.3.3 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.5.1 3.3.5.2 3.3.5.3 3.3.5.4 3.3.5.5 3.3.6 3.4 3.4.1 3.4.1.1 3.4.1.2 3.4.2 3.4.3 3.4.3.1 3.4.3.2 3.4.3.3 3.4.3.4 3.4.3.5 3.4.3.6 3.4.3.7 3.4.3.8 3.4.3.9 3.4.3.10 3.4.3.11 4 4.1 4.1.1 4.1.1.1 4.1.1.2 4.1.1.3 4.1.1.4 4.1.1.4.1 4.1.1.4.2 4.1.1.4.3 4.1.1.4.4 4.1.2 4.1.2.1 4.1.3 Page Standard I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 P MAI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Activation Initiated by Exchange (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Activation Initiated by Exchange (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Activation Initiated by Terminal (TE/LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 TIC Bus D-Channel Control in TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 S-Bus D-Channel Control in TEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 S-Bus D-Channel Control in LT-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 D-Channel Control in the Intelligent NT (TIC-and S-Bus) . . . . . . . . . . . . . . . . . . . . . 78 IOM(R)-2 Interface Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Maintenance Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Test Loop-Backs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Complete Loop-Backs (No. 2, No. 3, and No. A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Single Channel Loop-Backs (No. 4, No. B1/2, No. C) . . . . . . . . . . . . . . . . . . . . . . . . 87 Monitoring of Illegal Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Test Modes and System Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Test Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Test Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Pulse Mask Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 NT Transmitter Output/Receiver Input Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . 89 TE Transmitter Output/Receiver Input Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . 89 NT/TE Timing Extraction Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 TE Total Phase Deviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 TE and NT Longitudinal Conversion Loss (LCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TE and NT Output Signal Balance (OSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TE Frame Rate Info1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Loss and Regain of Frame Alignment (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 IOM(R)-2 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Timing Characteristics CEB (NT / LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Command/Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Monitor Procedure Timeout (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 MON-1, MON-2 Commands (S/Q Channel Access) . . . . . . . . . . . . . . . . . . . . . . . . 106 MON-8 Commands (Register Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 S/T-Interface Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Semiconductor Group 4 General Information Contents (cont'd) 4.1.4 4.1.4.1 4.1.4.2 4.1.4.3 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.3 4.3.1 4.3.1.1 4.3.1.2 4.3.1.2.1 4.3.1.2.2 4.3.1.2.3 4.3.1.3 4.3.1.3.1 4.3.1.3.2 4.3.1.4 4.3.2 4.3.2.1 4.3.2.2 4.3.2.2.1 4.3.2.2.2 4.3.2.2.3 4.3.2.3 4.3.2.3.1 4.3.2.3.2 4.3.2.4 4.3.3 4.3.3.1 4.3.3.2 4.3.3.2.1 4.3.3.2.2 4.3.3.2.3 4.3.3.3 4.3.3.3.1 4.3.3.3.2 4.3.3.4 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Page Maintenance Auxiliary Interface (MAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 I/O Specific Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Standard I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 P MAI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Complete Activation Initiated by Exchange (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . 123 Complete Activation Initiated by Exchange (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Complete Activation Initiated by Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 State Machine TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 TE/LT-T Modes State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 TE/LT-T Modes Transition Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 C/I Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Pin States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 S/T-Interface Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Transmitted Signals and Indications in TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . 133 C/I Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 S/T-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 States TE/LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 LT-S Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 LT-S Mode Transition Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 C/I Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Pin States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 S/T-Interface Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Transmitted Signals and Indications in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . 139 C/I Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 S/T-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 States LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 NT Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 NT Mode Transition Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 C/I Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Pin States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 S/T-Interface Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Transmitted Signals and Indications in NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 143 C/I Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 S/T-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 States NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 C/I Command RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Hardware Reset RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Push/Pull Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Initializing LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Semiconductor Group 5 General Information Contents (cont'd) 4.5 4.5.1 4.5.1.1 4.5.1.2 4.5.2 4.6 4.6.1 4.6.1.1 4.6.1.2 4.6.2 4.6.2.1 4.7 4.7.1 4.7.1.1 4.7.1.2 4.7.2 4.8 4.8.1 4.8.2 4.8.3 4.8.3.1 4.8.3.2 4.8.4 4.8.5 5 5.1 5.2 5.3 5.4 5.5 6 7 7.1 7.2 7.3 Page Maintenance Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Test Loop-Backs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Complete Loop-Backs (No. 2, No. 3, and No. A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Single Channel Loop-Backs (No. 4, No. B2, No. C) . . . . . . . . . . . . . . . . . . . . . . . . 148 Monitoring of Illegal Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Clock Generation and Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 NT and LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Transmit and Receive PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Jitter Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 LT-T and TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Receive PLL in TE and LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Elastic Buffers in LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Jitter Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Output Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Recommended Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Analog Line Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 S/T-Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 S/T-Interface Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Line Overload Protection (Transmitter, Receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Transmitter Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Receiver Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 165 166 166 167 168 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delta and Errata Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Components Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 173 177 181 SICOFI(R), SICOFI(R)-2, SLICOFI(R), ARCOFI(R), EPIC(R)-1, EPIC(R)-2, IPAT(R), IOM(R), IOM(R)-1, IOM(R)-2, ISAC(R)-S, ISAC(R)-P, IDEC(R) are registered trademarks of Siemens AG. ELICTM, MUSACTM, MUSACTM-A, OCTATTM-P are trademarks of Siemens AG. Semiconductor Group 6 General Information Table of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Page PEB 2081 SBCX in P-DIP-28 and P-LCC-28-R Packages . . . . . . . . . . . . . . . . . . . . 12 Logic Symbol of the SBCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block Diagram of the SBCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating Modes of the SBCX in the ISDN Basic Access Architecture . . . . . . . . . . . 16 ISDN Voice/Data Terminal using the IOM(R)-2 Terminal Architecture (TE) . . . . . . . . . 17 SBCX in TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Basic Network Terminator (NT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SBCX in NT-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 NT-Star Configuration with 8 TEs Connected Point-to-Point . . . . . . . . . . . . . . . . . . . 21 Figure 10: NT-Star Configuration with 2 TEs Connected Point-to-Point and 6 TEs Connected via an Extended Passive Bus . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11: NT-Star Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12: SBCX in NT-Star Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13: Micro Controlled NT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14: Intelligent NT Providing both Terminal (voice/data) and Network Terminating Functions (S/T-interface) . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15: SBCX in LT-S Mode for Intelligent NT Configurations . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16: IOM(R)-2 Line Card Architecture (LT-S) with One D-Channel Controller per Line . . . . 27 Figure 17: SBCX in LT-S Mode for Basic Line Card Configuration . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 18: IOM(R)-2 Line Card Architecture (LT-S only) with One D-Channel Controller per up to Eight Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 19: SBCX in LT-S Mode for Star Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 20: PBX Architecture (LT-T) with One D-Channel Controller per Line . . . . . . . . . . . . . . . 31 Figure 21: PBX-Configuration Requiring S/G Bit Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 22: SBCX in LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 23: Clock Generation for TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 24: Clocks Generation in NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 25: Clock Generation in LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 26: Clock Generation in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 27: S/T-Interface Point-to-Point Configuration ("TR" stands for the 100 Terminating Resistor). . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 28: S/T-Interface Extended Passive Bus Configuration ("TR" stands for the 100 Terminating Resistor). . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 29: S/T-Interface Short Passive Bus Configuration ("TR" stands for the 100 Terminating Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 30: SBCX Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 31: IOM(R)-2 Interface Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 32: Basic Channel Structure of IOM(R)-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 33: Multiplexed Frame Structure of the IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . 47 Semiconductor Group 7 General Information Table of Figures (cont'd) Page Figure 34: Definition of the IOM(R)-2 Channels in a Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 35: C/I-Channel Use with the ICC (all data values hexadecimal) . . . . . . . . . . . . . . . . . . 52 Figure 36: C/I-Channel Use with the EPIC(R) (all data values hexadecimal) . . . . . . . . . . . . . . . . 53 Figure 37: Monitor Channel Handling with ICC (all data values hexadecimal) . . . . . . . . . . . . . . 55 Figure 38: Monitor Channel Handling with EPIC(R) (all data values hexadecimal) . . . . . . . . . . . . 57 Figure 39: S Multiframe Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 40: S-Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 41: D-Channel Access Control on TIC Bus and S Bus . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 42: Data Flow for Collision Resolution Procedure in Intelligent NT . . . . . . . . . . . . . . . . . 80 Figure 43: Intelligent NT-Configuration for IOM(R)-2 Channel Switching . . . . . . . . . . . . . . . . . . . 81 Figure 44: Test Loop-Backs Supported by PEB 2081 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 45: External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 46: Single Loops of the SBCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 47: IOM(R)-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 48: S/T-Interface Multi-Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 49: Timing of the IOM(R)-2 Interface in TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 50: Timing of the IOM (R)-2 Interface in NT / LT-S and LT-T Mode . . . . . . . . . . . . . . . . . . 96 Figure 51: Timing of the CEB Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 52: Timing of the CEB Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 53: Functional Timing of the CEB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 54: Handshake Protocol with a 2-Byte Monitor Message/Response . . . . . . . . . . . . . . . 103 Figure 55: Abortion of Monitor Channel Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 56: S/T -Interface Line Code (without code violation) . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 57: Frame Structure at Reference Points S and T (ITU I.430) . . . . . . . . . . . . . . . . . . . . 115 Figure 58: Dynamic Characteristics of P Interface Write Access . . . . . . . . . . . . . . . . . . . . . . 120 Figure 59: Dynamic Characteristics of P Interface Read Access . . . . . . . . . . . . . . . . . . . . . . 120 Figure 60: Complete Activation Initiated by Exchange (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 61: Complete Activation Initiated by Exchange (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 62: Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 63: Deactivation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 64: Deactivation of the IOM(R)-2 Interface in the NT (DCL = 512 kHz) . . . . . . . . . . . . . . 127 Figure 65: State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 66: State Transition Diagram in TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 67: State Diagram of the TE/LT-T Modes, Unconditional Transitions . . . . . . . . . . . . . . 131 Figure 68: State Transition Diagram in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 69: NT Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 70: Dynamic Characteristics of Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 71: Clock System of the SBCX in NT and LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Semiconductor Group 8 General Information Table of Figures (cont'd) Page Figure 72: Receive PLL of the SBCX in TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 73: Receive PLL of the SBCX in LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 74: Phase Relationships of TE Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 75: Recommended Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 76: Receiver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 77: Receiver Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 78: Transmitter Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 79: Dynamic Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 80: External Circuitry Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Figure 81: External Circuitry Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Figure 82: Transformer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 83: Test Condition for Maximum Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Figure 84: Destruction Limits Transmitter Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 85: Destruction Limits Receiver Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 86: Power Supply Rejection SBCX Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 87: State Transition Diagram in TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Figure 88: State Diagram of the LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Figure 89: NT Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Semiconductor Group 9 General Information Introduction The PEB 2081 S/T Bus Interface Circuit Extended (SBCX) implements the four-wire S/T-interface used to link voice/data ISDN terminals, network terminators and PABX trunk lines to a Central Office. The SBCX provides the electrical and functional link between the analog S/T-interface according to ITU recommendation I.430, ETS 300 012 and T1.605 Basic User Network Interface Specification respectively, and the ISDN Oriented Modular interface Rev. 2 (IOM-2). This manual is divided into 6 major sections. Compared to previous data sheets for the S transceiver, the organization of the data sheet for version 3.4 has been modified in order to make information more readily available to the user. Section 1 gives the user an introduction to the PEB 2081 Vers. 3.4. It contains information about the functional blocks, features and pinning of the SBCX. Section 2 provides an overview of typical ISDN applications and demonstrates how these applications can be realized with the PEB 2081 Vers. 3.4. Sections 3 and 4 are identical in structure. Both cover the major S transceiver topics "Interfaces", "Control Procedures" and "Maintenance Functions". Section 3 gives the user an overview on the discussed topics without going into technical details. It is intended as an application guide where the user can quickly look up how the registers of ICC, EPIC and SBCX Vers. 3.4 need to be programmed in order to initiate the desired action. Section 4 is dedicated to detailed technical information. Status diagrams, state descriptions, algorithms, dynamic characteristics are to be found here. Section 4 thus is intended for the user who seeks specific technical information. Section 5 summarizes all electrical, section 6 all environmental characteristics. Semiconductor Group 10 S/T Bus Interface Circuit Extended PEB 2081 1 Features the following specifications: - ITU Recommendation I.430 - ETS 300 012 - ANSI T1.605 192 kbit/s transmission rate Pseudo-ternary coding with 100 % pulse width Activation and deactivation procedures Extended loop-length up to 2 km q Full duplex 2B+D S/T-interface transceiver according to q q q q P-LCC-28-1 IOM(R)-2 Interface q Optimized for operation in conjunction with IEC-Q, IBC, ICC, EPIC and IDEC telecom ICs q Handling of commands and indications contained in the IOM-2 C/I channel for activation, deactivation and testing q Switching of test-loops Modes q q q q TE NT LT-T LT-S : : : : Terminal Mode Network termination connected to IEC-Q Trunk mode in private exchange Line termination in public or private exchanges P-DIP-28-3 Special Features q q q q q q q Fully compliant NT2 trunk mode including multipoint operation Frame alignment with absorption of phase wander in NT2 network side applications D channel access control, also in trunk application Access to S and Q bits of S/T-interface (S1, S2 and Q channel) Software controlled maintenance interface (I/O ports) Switching of test loops Advanced CMOS technology with low power consumption: power down max. 4 mW operational max. 60 mW Ordering Code Q67100-H6581 Q67100-H6580 Package P-DIP-28-3 P-LCC-28-1 Type PEB 2081P PEB 2081N Semiconductor Group 11 11.96 1.1 Pin Configuration (top view) V DD SX 1 SX 2 1 2 3 4 5 6 7 8 9 P-DIP-28-3 28 27 26 25 24 23 MAI 7 VSS SR 2 SR 1 V SS MAI 3 X3 RST MAI 2 FSC MAI 1 DCL IDP1 IDP 0 MAI 0 VDD MAI6 X1 MAI 5 X2 MAI 4 X0 XTAL 2 XTAL 1 MODE PEB 2081 SBCX 22 21 20 19 18 17 16 15 ITP03973 10 11 12 13 14 Figure 1 PEB 2081 SBCX in P-DIP-28-3 and P-LCC-28-1 Packages Semiconductor Group 12 Features 1.2 Pin No. 11 Pin Definition and Functions Symbol DCL Input (I) Function Output (O) I/O Data Clock The frequency is equal to twice the data rate on the IOM-2 interface. LT-S, LT-T, NT: clock input 512 kHz to 8192 kHz TE: clock output 1536 kHz Frame Synchronization Clock LT-S, LT-T, NT: clock input 8 kHz TE: clock output 8 kHz IOM-2 data port 0; open drain with an external pull up resistor, otherwise push/pull IOM-2 data port 1; open drain (if external pull up resistor at IDP0), otherwise push/pull Differential S/T-interface receiver signal input Differential S/T-interface receiver signal input Differential S/T-interface positive transmitter output Differential S/T-interface negative transmitter output Setting of either LT modes or NT and TE mode Specific function pins dependent from the selected operating mode 9 FSC I/O 13 12 25 26 2 3 15 6 20 22 18 28, 23, 21, 19 5 8, 10, 14 24 1 4 27 7 16 17 IDP0 IDP1 SR1 SR2 SX1 SX2 MODE X3 X2 X1 X0 MAI (7:4) MAI 3 MAI (2:0) I/O I/O I I O O I I/O I I I/O O I I/O I I I I I I O Maintenance Auxiliary Interface; output pins Maintenance Auxiliary Interface; input pin Maintenance Auxiliary Interface; input/output pins Power supply + 5 V 5 % Power supply + 5 V 5 % Ground Ground Reset, low active Connection for external crystal, or input for external clock generator Connection for external crystal, not connected, when an external clock generator is used VDD VDD VSS VSS RST XTAL1 XTAL2 Semiconductor Group 13 Features 1.3 Logic Symbol IOM R -2 Interface DCL FSC IDP 0 IDP 1 SX 1 2:1 SX 2 Maintenance Auxiliary Interface MAI (7 : 0) SR1 2:1 PEB 2081 (SBCX) SR 2 MODE Mode Mode Specific Functions X3 X2 X1 X0 XTAL1 7.68 MHz XTAL 2 VDD VSS RST ITL03972 +5V GND Figure 2 Logic Symbol of the SBCX Semiconductor Group 14 Features 1.4 Functional Block Diagram FSC DCL SX 1 SX 2 Transmit Buffer D-Channel Control SR 1 SR 2 DPLL ITA03958 IOM Interface Logic R IPD 1 IPD 0 Activation Control S/Q Bit Handler Receive Buffer Figure 3 Block Diagram of the SBCX Semiconductor Group 15 System Integration 2 System Integration and Applications The SBCX implements the four-wire S- and T-interfaces used in the ISDN basic access. By programming the corresponding operating mode it may be used at both ends of these interfaces. The operating modes are: q ISDN terminals (TE) q ISDN network termination (NT) for a link between the four-wire S/T-interface and the two-wire U-interface q ISDN subscriber line termination (LT-S) q ISDN trunk line termination (LT-T); (PBX connection to Central Office). The basic use of these modes is shown in the following figure, where the usual nomenclature as defined by the ITU for the basic access functional blocks and reference points, is used. S TE(1) LT-S TE(8) Network Terminator (NT) S TE (1) NT T TE(8) LT-S NT 2 LT-T NT ITS04492 U NT 1 NT 1 Figure 4 Operating Modes of the SBCX in the ISDN Basic Access Architecture The NT equipment serves as a converter between the U-interface at the exchange and the S-interface at the user premises. The NT may consist of either an NT1 or an NT1 together with an NT2 connected via the T-interface which is physically identical to the S-interface. The NT1 is a direct transformation between layer 1 of S and layer 1 of U. NT2 may include higher level functions like multiplexing and switching as in a PBX. Semiconductor Group 16 System Integration 2.1 2.1.1 Operational Modes and System Integration TE Application In the terminal several IOM-2 compatible devices can be connected to the IOM-2 bus structure (e.g. PEB 2070 ISDN Communications Controller (ICC), PSB 2161 Audio Ringing Codec Filter (ARCOFI(R)), PSB 2163 Audio Ringing Codec Filter (ARCOFI(R)SP) and PSB 2110 ISDN Terminal Adapter Circuit (ITAC(R))). The ICC allows access to IOM-2 bus by the microcontroller. The SBCX is controlled via MON0 channel, the other devices via MON1 channel of the IOM-2 bus. IOM -2 Terminal Interface R PEB 2081 SBCX PSB 2110 ITAC PSB 2161 ARCOFI R -BA or PSB 2163 ARCOFI R -SP PEB 2070 ICC C ITS08392 Figure 5 ISDN Voice/Data Terminal using the IOM(R)-2 Terminal Architecture (TE) Semiconductor Group 17 System Integration 1.536 MHz 8 kHz 11 9 13 12 16 DCL FSC IDP 0 IDP 1 XTAL1 XTAL 2 SX 1 2 20...40 20...40 2 :1 TR Transmit Pair SX 2 3 33 pF S/T Interface 25 10 k 10 k 2 :1 TR Receive Pair 7.68 MHz 33 pF 0V 0V 0V +5V 10 F GND 0/5 V 768 kHz 17 6 20 22 18 15 1 24 4 27 7 SR1 X3 X2 X1 X0 Mode PEB 2081 SR 2 MAI0 MAI 1 MAI 2 MAI 3 MAI 4 MAI 5 MAI 6 MAI 7 ITS05101 26 14 10 8 5 19 21 23 28 PCK CON 0/5 V Maintenance Auxiliary Interface VDD VDD VSS VSS RST S/G Figure 6 SBCX in TE Mode Semiconductor Group 18 System Integration 2.1.2 ISDN Network Termination (NT1) The S-interface is a four-wire interface for connecting ISDN Terminal Equipment (TE) and Terminal Adapter (TA) to the Network Termination (NT). From here a twisted pair interfaces to the exchange. The Network Terminator interfaces the four-wire to the two-wire interface. A basic Network Terminator (NT1) can be built using the SBCX together with the PEB 2091 ISDN Echo-Cancellation Circuit (IEC-Q1) or in case of a private exchange the PEB 2095 ISDN Burst Transceiver Circuit (IBC). All information between S- and U-interface is handled automatically between the layer-1 devices IEC-Q (or IBC) and the SBCX. PEB 2081 SBCX IOM R -2 Terminal Interface PEB 2091 IEC-Q1 ITS03977 Figure 7 Basic Network Terminator (NT1) Semiconductor Group 19 System Integration 512 kHz 8 kHz 11 9 13 12 16 17 DCL FSC IDP 0 IDP 1 XTAL 1 XTAL 2 SX 1 2 20...40 20...40 2 :1 TR Transmit Pair SX 2 3 System Clock from U-Interface 7.68 MHz S/T Interface 25 10 k 10 k NT-STAR MFD TM 1 TM 2 MPR 4 MPR 5 MPR 6 MPR 7 5V 0/5 V 0/5 V 0/5 V 2 :1 TR Receive Pair 5V 5V 0V 0/5 V 0V +5V CEB 6 20 22 18 15 1 24 SR1 X3 X2 X1 X0 Mode PEB 2081 SR 2 MAI 0 MAI 1 MAI 2 MAI 3 MAI 4 MAI 5 MAI 6 MAI 7 ITS05102 26 14 10 8 5 19 21 23 28 VDD VDD VSS VSS RST 10 F GND 0/5 V 4 27 7 Maintenance Auxiliary Interface Figure 8 SBCX in NT-Mode 2.1.3 ISDN Network Terminator (NT1) in Star Configuration A NT-star configuration is used when it is not possible to connect all terminals with a short or extended passive bus configuration. This may be the case if the terminal locations are too far apart to comply to the restrictions specified for short or extended passive bus systems. In this application the IOM-2 interface operates with a DCL frequency of 512 kHz. Downstream data will be transmitted to all connected TEs. The upstream data from all TE's will be wired-ANDed on the IOM-2 interface. The NT-star mode ensures under these circumstances, the correct D-channel collision detection as well as the correct activation behavior (see also section 3.3). Both point-to-point or passive bus configurations are allowed. A combination of these two configurations is also possible, see figure 9 and 10. Semiconductor Group 20 System Integration TE 2 km TE 2 km TE 2 km TE 2 km SBCX SBCX SBCX SBCX IOM -2 R IEC-Q U-Interface TE 2 km SBCX SBCX SBCX SBCX NT 2 km TE 2 km TE 2 km TE ITC05103 Figure 9 NT-Star Configuration with 8 TEs Connected Point-to-Point TE 2 km TE TE TE 1.5 km SBCX SBCX IOM -2 R IEC-Q U-Interface TE TE TE SBCX NT 2 km TE ITC05104 Figure 10 NT-Star Configuration with 2 TEs Connected Point-to-Point and 6 TEs Connected via an Extended Passive Bus Semiconductor Group 21 System Integration PEB 2081 SBCX NT/LT-S IOM R -2 Terminal Interface CEB PEB 2091 IEC-Q1 PEB 2081 SBCX NT/LT-S ITS03976 Figure 11 NT-Star Configuration Semiconductor Group 22 System Integration 512 kHz 8 kHz 11 9 13 12 16 17 DCL FSC IDP 0 IDP 1 XTAL 1 XTAL 2 SX 1 2 20...40 20...40 2 :1 TR Transmit Pair SX 2 3 System 7.68 MHz Clock 5V 5V 0V 0/5 V 0V +5V 10 F GND 0/5 V S/T Interface 25 10 k 10 k NT-STAR MFD TM 1 TM 2 0V 0/5 V 5V 5V 2 :1 TR Receive Pair CEB 6 20 22 18 15 1 24 4 27 7 SR1 X3 X2 X1 X0 Mode PEB 2081 SR 2 MAI0 MAI 1 MAI 2 MAI 3 MAI 4 MAI 5 MAI 6 MAI 7 ITS05105 26 14 10 8 5 19 21 23 28 VDD VDD VSS VSS RST Maintenance Auxiliary Interface Figure 12 SBCX in NT-Star Mode Semiconductor Group 23 System Integration 2.1.4 ISDN Network Terminator Using IOM(R)-2 Architecture (Intelligent NT) The IOM-2 architecture allows to build a micro controlled NT using additionally the ICC and operating the IEC-Q (or IBC) in the IOM-2 terminal mode. The ICC provides software controlled layer-1 maintenance function such as programming the SBCX via the monitor channel. The SBCX is set to LT-S mode and is operated in the IOM-2 channel 1 of the IOM-2 terminal architecture. For that purpose the SBCX offers the possibility of changing the state machine from LT-S mode to NT mode (refer to FSMM-bit of the configuration register) in order to behave like a Network Termination with only two devices (NT1). The SBCX provides the required IOM-2 channel switching functions (B1, B2, D and C/I) for this application. To ensure a proper wake up procedure of a micro controlled NT being in power down (case of a deactivated line) the asynchronous timing bit (AST-bit of the loop-back register) should be set. The U- and S/T-interface maintenance data is conveyed via the IOM-2 interface's monitor channel to the ICC. PEB 2081 SBCX IOM R -2 Terminal Interface 1.536 MHz PEB 2091 IEC-Q1 PEB 2070 ICC C ITS03978 Figure 13 Micro Controlled NT Configuration Semiconductor Group 24 System Integration The S-interface is the standard ISDN subscriber interface, but in a PBX environment also an U-interface (e.g. IBC or IEC-Q) may be used for the connection of a subscriber resulting in an U-interface terminal with an S/T-extension (Intelligent NT). The Intelligent NT can be seen as an enhancement of the micro controlled NT. In this case the SBCX is treated as an additional IOM-2 device. The ICC accesses the IBC or IEC-Q via MON0 channel, the other devices via MON1 channel. The functionality of such a configuration includes D-channel collision resolution in upstream direction (TIC bus) and IOM-2 channel switching functions for internal communication. PEB 2081 SBCX IOM -2 Terminal Interface R PEB 2091 IEC-Q1 PSB 2110 ITAC PSB 2163 ARCOFI -SP R PEB 2070 ICC C ITS03979 Figure 14 Intelligent NT Providing both Terminal (voice/data) and Network Terminating Functions (S/T-interface) Semiconductor Group 25 System Integration 1536 kHz 8 kHz 11 9 13 12 DCL FSC IDP 0 IDP 1 XTAL 1 XTAL 2 SX 1 2 20...40 20...40 2 :1 TR Transmit Pair SX 2 3 System Clock 7.68 MHz 16 17 S/T Interface 25 10 k 10 k NT-STAR 5V Maintenance Auxiliary Interface 2 :1 TR Receive Pair 5V 0V 0V 5V 5V +5V CEB TS 2 TS 1 TS 0 6 20 22 18 15 1 24 SR1 X3 X2 X1 X0 Mode PEB 2081 SR 2 MAI0 MAI 1 MAI 2 MAI 3 MAI 4 MAI 5 MAI 6 MAI 7 ITS05106 26 14 10 8 5 19 21 23 28 VDD VDD VSS VSS RST 10 F GND 0/5 V 4 27 7 Figure 15 SBCX in LT-S Mode for Intelligent NT Configurations Semiconductor Group 26 System Integration 2.1.5 Line Card Application (one D-channel controller per line) The SBCX supports a line card implementation both in an ISDN Subscriber Line Termination LT-S) and in an ISDN Trunk Line Termination (LT-T) using e.g. the PEB 2055 Extended PCM Interface Controller (EPIC(R)-1). Up to eight devices can be connected to the IOM-2 interface. This application requires a data clock of 4.096 MHz. The standard implementation of a S/T-interface line card includes one D-channel controller, e.g. PEB 2075 ISDN D-Channel Exchange Controller (IDEC(R)), per line for decentralized D-channel handling. Figure 16 illustrates this configuration for line cards on the exchange side. IOM -2 Interface R 4096 kHz PCM PEB 2081 1. SBCX PEB 2055 EPIC R HWs PEB 2081 2.SBCX PEB 2075 IDEC R PEB 2075 IDEC R PEB 2081 8.SBCX P SAB HSCX ITS05107 Signaling Highway Figure 16 IOM(R)-2 Line Card Architecture (LT-S) with One D-Channel Controller per Line Semiconductor Group 27 System Integration 4096 kHz 8 kHz 11 9 13 12 16 DCL FSC IDP 0 IDP 1 XTAL1 XTAL 2 SX 1 2 20...40 20...40 2 :1 TR Transmit Pair SX 2 3 33 pF S/T Interface 25 10 k 10 k NT-STAR 5V Maintenance Auxiliary Interface 2 :1 TR Receive Pair 7.68 MHz 33 pF 5V 0/5 V 0/5 V 0/5 V +5V +5V 10 F GND 0/5 V CEB TS 2 TS 1 TS 0 17 6 20 22 18 15 1 24 4 27 7 SR1 X3 X2 X1 X0 Mode PEB 2081 SR 2 MAI 0 MAI 1 MAI 2 MAI 3 MAI 4 MAI 5 MAI 6 MAI 7 ITS05108 26 14 10 8 5 19 21 23 28 VDD VDD VSS VSS RST Figure 17 SBCX in LT-S Mode for Basic Line Card Configuration Semiconductor Group 28 System Integration 2.1.6 Line Card Application (one D-channel controller for eight lines) This configuration is used under the same circumstances as described in section 2.1.3 "NT1 Star Configuration". Refer to this section for additional information. Figure 18 and figure 19 illustrate the principle and its realization in line card applications. IOM -2 Interface 512 kHz R PEB 2081 1.SBCX 4 PEB 2070 ICC PEB 2055 EPIC R PEB 2081 2. SBCX X3: CEB PEB 2081 8. SBCX P ITS03981 5V 5V Figure 18 IOM(R)-2 Line Card Architecture (LT-S only) with One D-Channel Controller per up to Eight Lines Semiconductor Group 29 System Integration 5V 512 kHz 8 kHz 33 pF 7.68 MHz 1) 33 pF 5V 0V 0V 0V 5V +5V 10 F GND 0/5 V CEB TS 2 TS 1 TS 0 11 9 13 12 16 17 DCL FSC IDP 0 IDP 1 XTAL1 XTAL 2 SX 1 2 20...40 20...40 2 :1 TR Transmit Pair SX 2 3 S/T Interface 25 10 k 10 k NT-STAR 0V Maintenance Auxiliary Interface 2 :1 TR Receive Pair 6 20 22 18 15 1 24 4 27 7 SR1 X3 X2 X1 X0 Mode PEB 2081 SR 2 MAI 0 MAI 1 MAI 2 MAI 3 MAI 4 MAI 5 MAI 6 MAI 7 ITS05109 26 14 10 8 5 19 21 23 28 VDD VDD VSS VSS RST 1) Optionally system clock may be used Figure 19 SBCX in LT-S Mode for Star Configuration Semiconductor Group 30 System Integration 2.1.7 Private-Branch-Exchange Application (one D-channel controller per line) The SBCX also supports ISDN-PBX configurations in its LT-T (Line Termination-Trunk) mode. By providing internal buffers in this mode, the device is able to compensate phase deviations between the two clock systems on the S-interface and the IOM-2 interface (in PBX system the PEB 2081 is slave with respect to these two clock systems). Specific requirements regarding the clock generation in a PBX system are described in section 2.3 "Clock Generation". PCM 4096 kHz IOM -2 Interface R PEB 2055 EPIC R PEB 2081 1. SBCX HWs PEB 2075 IDEC R PEB 2075 IDEC R PEB 2081 2.SBCX MAI 5 : S/G Bit Signaling Highway SAB 82525 HSCX P PEB 2081 8. SBCX ITS03980 Figure 20 PBX Architecture (LT-T) with One D-Channel Controller per Line Semiconductor Group 31 System Integration D-channel processing is handled by a separate controller for each line as was the case for line card applications. In order to guarantee correct D-channel access on the S-interface when additional terminals are connected to the same S-bus, an external "D-channel access monitor bit" ( = S/G bit) ^ is provided in this mode. A system where this bit must be evaluated for correct D-channel access is shown in the following figure. In this configuration the D-channel controller of PBX No. 1 is informed via the S/G bit when the terminal occupies the D-channel on the S-interface. In case a point-to-point configuration is used to connect a single PBX to an exchange the S/G line is not required. Please refer to section 3.2.3.1 for additional information regarding the use of the S/G bit. PBX No.1 5V NT1 SBCX LT-T SBCX NT IDEC R IDEC R S/G SBCX LT-T SBCX NT ISAC -S TE IOM R -2 Terminal R ARCOFI R ITS05110 Figure 21 PBX-Configuration Requiring S/G Bit Evaluation Semiconductor Group 32 System Integration 33 pF IOM R -2 Clock Generator 33 pF 0/5 V 0/5 V 0/5 V 5V +5V 4096 kHz 11 8 kHz 9 13 12 16 7.68 MHz 17 DCL FSC IDP 0 IDP 1 XTAL1 XTAL 2 SX 1 2 20...40 20...40 2 :1 TR Transmit Pair SX 2 3 S/T Interface SR1 25 10 k 10 k 2 :1 TR Receive Pair System Clock 1536 kHz TS 2 TS 1 TS 0 6 20 22 18 15 1 24 X3 X2 X1 X0 Mode PEB 2081 SR 2 MAI0 MAI 1 MAI 2 MAI 3 MAI 4 MAI 5 MAI 6 MAI 7 ITS05111 26 14 10 8 5 19 21 23 28 CON 0/5 V Maintenance Auxiliary Interface VDD VDD VSS VSS RST 10 F GND 0/5 V 4 27 7 S/G Figure 22 SBCX in LT-T Mode Semiconductor Group 33 System Integration 2.2 Setting Operating Modes Tables 1-2 illustrate which modes are supported by the PEP 2081 version 3.4 and how they can be configured by the user. Table 1 gives an overview of pin signals and the register configuration. For the description of MAI pins it was assumed, that for the initial mode, the "I/O specific" mode was selected. Refer to chapter 4.1.4 for details on the MAI interface options. It is possible to change the mode of a device during operation by pin strapping (e.g. for test purposes) if the mode change is followed by a hardware reset. A hardware reset sets all registers to their initial value. Table 1 Modes of Operation Configuration LT-S Point-Point/Bus NT Point-Point/Bus LT-T TE Pin Mode X0 X1 X2 X3 MAI0 MAI1 MAI2 MAI3 MAI4 MAI5 MAI6 MAI7 FSC DCL 1 i:TS0 i:TS1 i:TS2 i/o:CEB i:NT-STAR i:MPR1 i:MPR2 i:MPR3 o:MPR4 o:MPR5 o:MPR6 o:MPR7 i:8 kHz i:512-8192 kHz 0 i:0/i:1 1) i:0 i:1 i/o:CEB i:NT-STAR i:MFD i:TM1 i:TM2 o:MPR4 o:MPR5 o:MPR6 o:MPR7 i:8 kHz i:512-8192 kHz 1 i:TS0 i:TS1 i:TS2 o:1536 kHz (3:2) i:MPR0 i:CON2) i:MPR2 i:MPR3 o:MPR4 o:S/G o:MPR6 o:MPR7 i:8 kHz i:512-8192 kHz 0 o:32/16 kHz (1:1) i:0 i:0 o:768 kHz (1:1) i:MPR0 i:CON3) i:MPR2 i:MPR3 o:MPR4 o:S/G if SGE = "1" o:MPR6 o:MPR7 o:8 kHz (1:2) o:1536 kHz (1:1) (cont'd) Note: 1) Choice for bus configuration (1 = bus). In LT-S mode only programmable. In NT mode programmable or pin strapping. Pin strapping has the higher priority. 2) CON-pin functionality is enabled if DH = "1" in the IOM-2 Channel register in LT-T mode. 3) CON-pin functionality is enabled if DH = "0" in the IOM-2 Channel register in TE mode. Semiconductor Group 34 System Integration Table 1 Modes of Operation (cont'd) Configuration LT-S Point-Point/Bus NT Point-Point/Bus LT-T TE Register Configuration Bit 0 (Mode) [0] Configuration Bit 1 (C/W/P) [0] Configuration Bit 5 (FSMM) [0] Configuration Bit 6 (MAIM) [0] SM/CI Bit 0 (MIO) [0] SM/CI Bit 2 (SGE) [0] IOM-2 Channel Bit 2 (DH) [0] 0 0/11) 0/1 0 0 0 0/14) 0/17) 0/11) 0/1 0 0 0 0/14) 1 0/12) 0 0 0 0 0/15) 0/17) 0/13) 0 0 0 0/18) 0/16) Notes: 1) Choice for bus configuration (1 = bus). In LT-S Mode only programmable. In NT mode programmable or pin strapping. Pin strapping has the higher priority. 2) Slip warning control. C/W/P = 0 will issue C/I "Slip" code warning after 50 s wander. C/W/P = 1 will issue the "Slip" code warning after 25 s. 3) PCK (pin X0) frequency select. C/W/P = 0 will issue a power converter clock frequency of 32 kHz, C/W/P = 1 will issue 16 kHz. 4) Select "1" for intelligent NT applications to ensure partial TIC Bus evaluation (see section 3.3.5.5). 5) Select "1" for point-to-multipoint configurations to ensure D-channel collision resolution according to ITU I.430 (see section 2.1.7 and 3.3.5.4). 6) For normal D-channel collision procedure program DH = "0". 7) 0: MAI pins I/O specific; 1: MAI pins only I/O. 8) In TE Mode pin MAI5 outputs a D-channel enable signal, which may be used by a general purpose HDLC controller for LAP D handling. The signal contiuously monitors the D-E channel status and provides a stop/ go information. [0] Initial register bit value after hard- or software reset. Semiconductor Group 35 System Integration Table 2 IOM(R)-2 Channel Assignment *) IOM(R)-2 Channel No. CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 TS2 0 0 0 0 1 1 1 1 TS1 0 0 1 1 0 0 1 1 TS0 0 1 0 1 0 1 0 1 Bit No. 0 ... 31 32 ... 63 64 ... 95 96 ... 127 128 ... 159 160 ... 191 192 ... 223 224 ... 255 Min. Freq. of DCL (kHz) 512 1024 1536 2048 2560 3072 3584 4096 Note: *) TS pins are read continuously (non-latching) after the supply voltage has reached its nominal value. Semiconductor Group 36 System Integration 2.3 Clock Generation Clock generation varies with the application. The following diagrams show what timing signals need to be generated for each SBCX mode and how system synchronization is obtained. 2.3.1 TE Mode XIN = 7.68 MHz X3 = 768 kHz FSC = 8 kHz DCL = 1536 kHz Synchr. ITS04198 TE Figure 23 Clock Generation for TE Mode In TE mode the PEB 2081 recovers the timing directly from the S-interface. A free running crystal or other clock source provides a 7.68 MHz base clock. The device synchronizes in TE Mode with a Receive PLL (RPLL) onto the S-interface by including 65 ns correction steps. Thus the issued IOM clocks and the clock signal on pin X3 are synchronous to the PTT master clock. Semiconductor Group 37 System Integration 2.3.2 NT Mode XTAL1 = 7.68 MHz FSC = 8 kHz NT DCL = 512 kHz Synchr. ITS05112 Figure 24 Clocks Generation in NT Mode In NT Mode the SBCX is supplied with synchronous IOM clocks and a synchronous base clock signal. These signals typically are generated by the upstream U-interface device (PEB 2091 or PEB 2095). In case no 7.68 MHz base clock signal is available, a 7.68 MHz crystal may be connected to XTAL1 and XTAL2. In this configuration the internal Transmit PLL (XPLL) synchronizes the freerunning crystal clock onto the FSC signal. If required DCL clock rates up to 8192 kHz may be used. However the PEB 2081 will operate in IOM channel 0 independently of the DCL frequency applied. Semiconductor Group 38 System Integration 2.3.3 LT-T Mode XIN = 7.68 MHz FSC = 8 kHz DCL = 512 ...4096 kHz XTAL1 LT-S 1 Synchr. FSC DCL % PLL Ref. Clock XIN = 7.68 MHz X3 = 1.536 MHz FSC DCL 1 Synchr. XIN = 7.68 MHz LT-T XTAL1 LT-S 2 Synchr. FSC DCL X3 = 1.536 MHz FSC DCL 2 Synchr. LT-T XIN = 7.68 MHz XTAL1 LT-S 8 Synchr. FSC DCL X3 = 1.536 MHz FSC DCL 8 Synchr. ITS08391 LT-T Figure 25 Clock Generation in LT-T Mode Semiconductor Group 39 System Integration In LT-T mode IOM-clock signals are not issued by the device but need to be generated externally. In order to ensure synchronous timing to the PTT-master clock, a PLL is used for generation of FSC and DCL (supplied to LT-T and LT-S devices) as well as of the 7.68-MHz system clock (LT-S only). Reference clock for the PLL is the PTT synchronous 1536-kHz signal from pin X3. Note: It may be necessary to use a multiplexer for the PLL reference clock because the X3 clock signal is synchronous to the PTT clock only if the corresponding line is activated. Otherwise the PLL reference must be supplied by the X3 clock from a different activated line. Semiconductor Group 40 System Integration 2.3.4 LT-S Mode 7.68 MHz FSC LT-S 1 DCL 7.68 MHz FSC LT-S 2 DCL FSC = 8 kHz DCL = 512 ...4096 kHz PLL PTT Reference Clock 7.68 MHz FSC LT-S 8 Synchr. ITS05201 DCL Figure 26 Clock Generation in LT-S Mode In LT-S mode the device synchronizes with the internal Transmit PLL (XPLL) the freerunning crystal clock onto the FSC signal. This ensures that transmission on the S-interface will be synchronous to the PTT clock. Semiconductor Group 41 System Integration 2.4 S/T-Interface Configurations The receiver of the SBCX exceeds the electrical requirements of the S/T-interface. An overview of the different wiring configurations is given in the following figures. The maximum length of a point-to-point configuration depends on the kind of cable installed. The maximum allowable line attenuation is 13 dB. However, the following figures give an idea of the performance of the SBCX. _ < 2 km IOM R SBCX TE/LT-T TR TR SBCX IOM R A1 NT/LT-S ITS03988 Figure 27 S/T-Interface Point-to-Point Configuration ("TR" stands for the 100 Terminating Resistor) _ < 1.5 km _ < 50 m TR A1 SBCX TE1 _ < 10 m An SBCX TE 8 TR SBCX IOM R NT/LT-S ITS03989 Figure 28 S/T-Interface Extended Passive Bus Configuration ("TR" stands for the 100 Terminating Resistor) _ < 150 m ... 250 m TR A1 SBCX TE1 _ < 10 m An SBCX TE 8 TR SBCX NT IOM R ITS03990 Figure 29 S/T-Interface Short Passive Bus Configuration ("TR" stands for the 100 Terminating Resistor) Semiconductor Group 42 Application Guide 3 3.1 Application Guide SBCX Device Architecture and General Functions The SBCX performs the layer-1 functions of the S/T-interface according to ITU recommendation I.430, ETS 300 012 and T1.605 Basic User Network Interface Specification, respectively. It can be used at all ends of the S/T-interface. The following figure depicts the device architecture. FSC DCL SX 1 Transmitter SX 2 Test Transmitter D-Channel Access Buffer Activation Control Buffer IOM -2 Interface Logic R IDP 1 IDP 0 SR1 SR 2 Amplifier and Filter Peak Detector Comparators S/Q Bits Buffer Level Detect Receive PLL Oscil. Transmit PLL ITS03991 Figure 30 SBCX Device Architecture Semiconductor Group 43 Application Guide The Common Functions for all Operating Modes are: q line transceiver functions for the S/T-interface according to the electrical specifications of q q q q q q ITU I.430 The pseudo-ternary pulse shaping which meets the I.430 pulse templates, is achieved with the integrated transmitter. The integrated receiver is designed to cope with all wiring configurations of the S/T-interface (point-to-point, passive bus, and extended passive bus). The maximum allowable line attenuation is 13 dB. conversion of the frame structure between the IOM-2 interface and S/T-interface conversion from/to binary to/from pseudo-ternary code access to S and Q bits The level detect block monitors the receive line and therefore initiates switching into power down or power up state. Mode Specific Functions are: receive timing recovery for point-to-point, passive bus and extended passive bus configuration S/T timing generation using IOM-2 timing synchronous to system, or vice versa D-channel access control and priority handling D-channel echo bit generation by handling of the common echo bit activation/deactivation procedures, triggered by primitives received over the IOM-2 interface or by INFOs received from the line q frame alignment in trunk application with maximum wander of 50 s q execution of test loops q q q q q Semiconductor Group 44 Application Guide 3.2 Interfaces Section 3.2 describes the interfaces supplied by the SBCX. Three interfaces are implemented: - IOM-2 Interface - S-Interface - Maintenance Auxiliary Interface 3.2.1 IOM(R)-2 Interface The IOM-2 interface is primarily used to interconnect telecommunication ICs. It provides a symmetrical full-duplex communication link, containing user data, control/programming and status channels. The SBCX communicates with other ISDN devices to realize OSI layer-1 functions (such as a U Transceiver) or upper layer functions (such as ICC, EPIC, ARCOFI and ITAC). The structure used follows the 2B + 1D-channel structure of ISDN. The ISDN user data rate of 144 kbit/s (B1 + B2 + D) on the S/T-interface is transmitted transparently in both directions over the interface. The D-channel switching may also be subject to the D-channel access procedure and collision detection and therefore is not fully transparent. The IOM-2 interface is a generalization and enhancement of the IOM (R)-1 interface. 3.2.1.1 IOM(R)-2 Frame Structure/Timing Modes The IOM-2 interface comprises two clock lines for synchronization and two data lines. Data is carried over Data Upstream (DU) and Data Downstream (DD) signals. The downstream and upstream direction are always defined with respect to the exchange. Downstream refers to information flow from the exchange to the subscriber and upstream vice versa respectively. The IOM-2 Interface Specification describes open drain data lines with external pull-up resistors. However, if operation is logically point-to-point, tristate operation is possible as well. The data is clocked by a Data Clock (DCL) that operates at twice the data rate. Frames are delimited by an 8-kHz Frame Synchronization Clock (FSC). FSC IOM R -2 Slave DCL DU DD ITS03992 IOM R -2 Master Figure 31 IOM(R)-2 Interface Structure Semiconductor Group 45 Application Guide Within one FSC period 32 bit to 512 bit are transmitted, corresponding to DCL frequencies from 512 kHz to 8.192 MHz. The SBCX needs no pin strapping to indicate the actual bit rate, because each rising edge of FSC resets the internal bit counter. Two optimized IOM-2 timing modes exist for: - Line card Applications - Terminal Applications Both the line card and terminal applications utilize the same basic frame and clocking structure, but differ in the number and usage of the individual channels. frame bits B1 8 B2 8 Monitor 8 D 2 Command/Indication 4 MR 1 MX 1 Figure 32 Basic Channel Structure of IOM(R)-2 Each frame consists of q two 64 kbit/s channels B1 and B2 q the monitor channel for transferring maintenance information between the layer-1 functional blocks (SBCX, IEC-Q, etc.) and the layer-2 controller (ICC, EPIC) q two bits for the 16 kbit/s D-channel q four command/indication (C/I) bits for controlling of layer-1 functions (activation/deactivation and additional control functions) by the layer-2 controller (ICC, EPIC). For a list of the C/I codes and their use refer to chapter 4. q two bits MR and MX for handling the monitor channel Semiconductor Group 46 Application Guide 3.2.1.1.1 IOM(R)-2 Interface Line Card Frame Structure The SBCX in line card applications (LT-S and LT-T) supports bit rates from 256 kbit/s to 4096 kbit/s corresponding to DCL frequencies from 512 kHz to 8.192 MHz. The typical IOM-2 line card applications comprises a DCL frequency of 4096 kHz with a nominal bit rate of 2048 kbit/s. Therefore eight channels are available, each consisting of the basic frame with a nominal data rate of 256 kbit/s. The length of the FSC high phase usually covers IOM-2 channel 0 (minimum FSC length is 2 DCL) unless synchronization of the S/T-interface multi-frame is desired. The SBCX is assigned to an individual channel by pin strapping. 125 s FSC DCL DU DD IOM CH0 IOM CH0 R R CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH4 CH5 CH5 CH6 CH6 CH7 CH7 CH0 CH0 B1 B2 MONITOR D C/I MM RX ITD04319 Figure 33 Multiplexed Frame Structure of the IOM(R)-2 Interface Semiconductor Group 47 Application Guide 3.2.1.1.2 IOM(R)-2 Interface Terminal Frame Structure In TE mode the SBCX provides a data clock DCL with a frequency of 1536 kHz. As a consequence the IOM-2 interface provides three channels each with a nominal data rate of 256 kbit/s. The SBXC only uses IOM-2 channel 0, and, for D-channel access control, the C/I field of IOM-2 channel 2. The downstream data (DD) are transferred on pin IDP0, the upstream data (DU) on pin IDP1. The remaining two IOM-2 channels are for the use of other devices (ARCOFI, ITAC) within the TE. 125 s FSC IOM DD B1 R Channel 0 MON0 C/I0 IC1 IOM R Channel 1 MON1 C/I1 IOM R Channel 2 C/I2 B1 B2 IC2 DU B1 B2 MON0 C/I0 IC1 IC2 MON1 C/I1 C/I2 B1 ITD04320 Figure 34 Definition of the IOM(R)-2 Channels in a Terminal Semiconductor Group 48 Application Guide - C/I0 in IOM(R) Channel 0: DU / DD D: C/I: D D C/I4 C/I3 C/I2 C/I1 MR MX two bits for the 16 kbit/s D-channel The four command/indication (C/I) bits are used for controlling of the layer-1 functions (activation/deactivation and additional control functions) by the layer-2 controller (ICC, EPIC). two bits MR and MX for handling the monitor channel 0 MR, MX: - C/I1 in IOM(R) Channel 1: DU / DD C/I6 C/I1 to C/I6 MR, MX: C/I5 C/I4 C/I3 C/I2 C/I1 MR MX are used to convey real status information between a layer-2 device (ICC) and various non layer-1 devices e.g. ARCOFI. two bits MR and MX for handling the monitor channel 1 - C/I2 in IOM(R) Channel 2: DU DD E: BAC-bit S/G-bit A/B-bit 1 E 1 E D-echo bits (Bus ACcessed), used by the layer-2 device (e.g. ICC). When the TIC bus is occupied the BAC-bit is low. (Stop/Go), available to the layer-2 devices (e.g. ICC) to determine if they can access the S bus D-channel (S/G = 1: stop, S/G = 0: go). (available/blocked), supplementary bit for D-channel control. (A/B = 1: D-channel available, A/B = 0: D-channel blocked). BAC S/G TBA2 A/B TBA1 1 TBA0 1 1 1 1 1 For more information also refer to the chapters TIC Bus Access and D-channel access control. Semiconductor Group 49 Application Guide 3.2.1.2 IOM(R)-2 Interface Command / Indicate Channel The Command/Indicate channel (C/I channel) is used to control the operational status of the SBCX and to issue corresponding indications. C/I channel codes serve as the main link between the SBCX and other external intelligence (layer-1 or layer-2 devices). In chapter 4.3 status diagrams for all selectable modes give information on the commands with which the current operational status may be left, and on indications issued in all states. The codes originating from the control devices are called "commands", those originating from the SBCX are referred to as "indications". Commands have to be applied continuously by the controller until the command is validated by the SBCX and the desired action has been initiated. Afterwards the command may be changed. An indication is issued permanently by the SBCX until a new indication needs to be forwarded. Because a number of states issue identical indications it is not possible to identify each state individually. The interpretation of C/I codes depends on the mode selected. Table 3 shows the abbreviations used for C/I commands and indications. The C/I channel can be disabled (Intelligent NT) by setting the CIH-bit in the IOM channel register. The C/I channel would then be accessible via the monitor channel (SM/CI register). In TE mode a second C/I channel can be used to convey real status information between by a layer 2 device (ICC) and various non layer-1 devices e.g. ARCOFI. The channel consists of six bits in each direction. For a list of the C/I codes and their use, refer to chapter 4. Semiconductor Group 50 Application Guide Table 3 C/I Abbreviations Code AI AI8 AI10 AIL AR AR8 AR10 ARL CVR DC DI DR MAIC PU RES RSY SLIP TIM TM1 TM2 Description Activation Indication Activation Indication with priority 8 Activation Indication with priority 10 Activation Indication Loop Activation Request Activation Request with priority 8 Activation Request with priority 10 Activation Request Loop Code Violation Received (far end) Deactivation Confirmation Deactivation Indication Deactivation Request Maintenance Auxiliary Interface Change Power Up Reset Resynchronizing Slip of Frame (frame jump) Timing Request Test Mode 1 (2-kHz test signal) Test Mode 2 (96-kHz test signal) The following examples illustrate the use of the C/I channel in combination with the PEB 2070 and the PEB 2055. Both examples assume that the device has been correctly initialized prior to starting the C/I code transfer. Semiconductor Group 51 Application Guide PEB 2070 and C/I-Channel Programming P STCR = 70 CIX0 = 47 C/I Channel Handler Select TIC-Bus Addr. No.7 Transmit C/ICommand "RESET" CISQ New C/I-Code received in Channels 0 or 1 Read New C/I-Code. The Code received was in Channel 0 No change of C/I-Code C/I = 0001b U-Transceiver Transfer to "RESET" State Send C/I-Indication "RES" ISTA = 04 C/I = 0000b CIR0 = 06 CICO = 1 CIR0 = 04 CICO = 0 ITD05305 Figure 35 C/I-Channel Use with the ICC (all data values hexadecimal) The STCR-register is programmed to allocate TIC-bus address 7 to the ICC. The C/I-command is transmitted with the CIX0-register (structure: 0 1 C/I C/I C/I C/I 1 1, bus access bit enabled). After the new C/I-command is loaded it is transmitted immediately. A change in the C/I-channel is indicated by an ISTA-interrupt (CISQ-bit). The new C/I-message can be read from register CIR0 (structure: 0 0 C/I C/I C/I CIC0 0 1). Bit CIC0 indicates that the new C/I-message was received in channel 0 for at least two consecutive frames. It is reset after the read operation. Semiconductor Group 52 Application Guide PEB 2055 and C/I-Channel Programming P MADR = C7 EPIC -1 C/I-Command "RESET" Select Port 0, Channel 0, C/I-Code Downstream Start Transmission SFI = 1 <- New C/I-Code was Received Read Port and TimeSlot No. where C/I was Received Select this Port/ Time-Slot for Reading (port 0, channel 0, C/I-code) Read C/I-Code Return C/I-Code in MADR-Register C/I = 0001 b C/I = 0001b R SBCX in TE Mode MAAR = 08 MACR = 48 ISTA = 40 Transfer to "RESET" State Send C/I-Indication "RES" CIFIFO = 88 MAAR = 88 MACR = C8 MADR = C7 ITD05304 Figure 36 C/I-Channel Use with the EPIC(R) (all data values hexadecimal) After the correct initialization of the EPIC, the C/I-code which is to be transmitted to the SBCX is written into the MADR-register (structure 1 1 C/I C/I C/I C/I 1 1). With the MAAR-register the EPIC is informed where to send this C/I-code (transmission direction, port number and time-slot number). For a description of this register please refer to the EPIC-manual, the example above sends the C/I-command to port 0, IOM-2 channel 0. MACR = 48 H starts the transmission of the command. If a change in one of the C/I-channels was observed, and ISTA-interrupt (bit SFI) is generated. Because the user does not know in which channel the change occurred, the location needs to be read from the CIFIFO-register. This address is copied via software into address register MAAR. After having started the read operation with MACR = C8H the C/I-message can be read from MADR (structure as described earlier). Semiconductor Group 53 Application Guide 3.2.1.3 IOM(R)-2 Interface Monitor Channel The monitor channel represents a second method to access SBCX specific features. Features of the monitor channel are supplementary to the C/I-channel. The SBCX uses the monitor channel for both, local programming and local functions (register access, e.g. MAI status) and S/Q maintenance bit information transfer. Monitor commands supported by the PEB 2081 divide into three categories. Each category derives its name from the first nibble (4 bits) of the one or two byte long message. All monitor messages representing similar functions are grouped together. Monitor functions of the SBCX can only be accessed by a control device (ICC, EPIC) in IOM-2 mode. The following chapters describe the principle of monitor handshake in IOM-2, internal safeguards against a blocking of the monitor channel as well as features supported. In case the IOM-2 Terminal structure is used, monitor channel 1 may be used by a codec device (e.g. ARCOFI). 3.2.1.3.1 Handshake Procedure IOM-2 provides a sophisticated handshake procedure for the transfer of monitor messages. For handshake control two bits are assigned to each IOM-frame (on IDP0 and IDP1). The monitor transmit bit (MX) indicates when a new byte has been issued in the monitor channel (active low). The transmitter postpones the next information until the correct reception has been confirmed. A correct reception will be confirmed by setting the monitor read bit (MR) to low. In order to send a monitor message from the control unit to the SBCX, the MX-bit on IDP1 and the MR-bit on IDP0 are used. In the opposite direction the SBCX handles the MX-bit of the IDP0-pin and watches the MR-bit of the IDP1-signal. Figure 37 illustrates monitor channel handling with the PEB 2070 (ICC), figure 38 demonstrates it with the PEB 2055 (EPIC-1). A two-byte message is sent from the control unit to the SBCX who acknowledges the receipt by returning a two-byte long message in the monitor channel. Semiconductor Group 54 Application Guide ICC and Monitor Channel Programming P ICC MX 01 MR 01 MX 01 MR 01 SBCX MOCR = 00 STAR MOSR = 00 MOX0 = 1. Byte MOCR = 03 MOCR = 02 MOX0 = 2. Byte MOSR = 02 MOCR = 0A Transmission inactive Transmitter inactive confirmation Store 1. Byte in Tx Register Transmit 1. Byte & Enable monitor interrupts Acknowledge received Store & Transmit 2. Byte Acknowledge received Set MX = 1 (EOM) Enable monitor Enable receive interrupts Monitor data received Read 1. Byte of response Ack. 1. Byte of response, enable interrupts Monitor data received Read 2. Byte of response & Ack. receipt EOM received Set MR = 1 Enable interrupts Read 1. Byte Transmit ack. Read 2. Byte Transmit ack. Transmit EOM ack. Transmit 1. Byte of confirmation MOSR = 08 MOR0 = 1. Byte MOCR = 0E MOSR = 08 MOX0 = 2. Byte MOSR = 04 MOCR = 0A STAR MOSR = 00 Transmit 2. Byte of confirmation Transmit EOM IDP 1 (SBCX) IDP 0 (SBCX) ITD04528 Figure 37 Monitor Channel Handling with ICC (all data values hexadecimal) Semiconductor Group 55 Application Guide The P starts the transfer procedure after having confirmed the monitor channel being inactive. The first byte of monitor data is loaded into the transmit register. Via the Monitor Control Register MOCR-monitor interrupts are enabled and control of the MX-bit is handed over to the ICC. Then transmission of the first byte begins. The SBCX reacts to a low level of the MX-bit on IDP1 by reading and acknowledging the monitor channel byte automatically. On detection of the confirmation, the ICC issues a monitor interrupt to inform the P that the next byte may be sent. Loading the second byte into the transmit register results in an immediate transmission (timing is controlled by ICC). The SBCX receives the second byte in the same manner as before. When transmission is completed, the ICC sends "End of Message" (MX-bit high). It is assumed that a monitor command was sent that needs to be confirmed by the SBCX (e.g. EOC commands). Therefore the PEB 2081 commences to issue a two-byte confirmation after an End-ofMessage indication from the ICC has been detected. The handshake protocol is identical to that of the ICC. The ICC notifies the P via interrupt when new monitor data has been received. The processor may then read and acknowledge the byte at a convenient instant. When confirmation has been completed, the SBCX sends "EOM". This generates a corresponding interrupt in the ICC. By setting the MR-bit to high, the monitor channel is inactive, the transmission is finished. PEB 2055 and Monitor Channel Programming: The EPIC-1 supports monitor transfers on a higher level than the ICC. Several modes are offered to support different types of monitor transfer. For communication with the SBCX, three are of special interest. - Transmit Only. This mode is required when the EPIC sends monitor messages but no confirmation is returned by the SBCX (e.g. MON8 "Configuration Register"). - Transmit and Receive. The EPIC transmits first and receives afterwards. Confirmations sent by the SBCX can be read (e.g. MON8 "Identification Register"). - Searching for Active Monitor Channels. Listens to the IOM-monitor channel and reads information issued by the SBCX autonomously (e.g. MON1 S/Q-messages). Nothing is transmitted by the EPIC. Unlike the ICC which had to respond to each change of the MR- and MX-bits individually (interrupt driven), the EPIC uses a FIFO for transmission and reception. The user therefore does not have to provide routines for the handshake protocol. The example of figure 37 demonstrates the use of EPIC-1 in the transmit-and-receive mode. As for the ICC it is assumed that the transferred monitor message will be followed by a two byte confirmation issued by the SBCX. Before programming the FIFO, it is verified that the FIFO is empty and write access is possible. All monitor data is loaded into the FIFO (two bytes), the transmission channel and mode are selected. Writing "CMDR = 08" starts transmission of the FIFO contents and enables monitor data reception. After both bytes have been transmitted, the confirmation from the SBCX is read into the FIFO. After completion of the transfer an interrupt is generated. If the operation was successful, "STAR = 26" will indicate that data is loaded and the read access is enabled (in addition it is indicated that the PCM-synchronization status is correct). Following the readout of the confirmation bytes, the FIFO is cleared and the write access is selected again with the CMDR-register ("CMDR = 01"). The handshake timing for byte transfer is identical to that described for the ICC. Both devices (EPIC and SBCX) handle it automatically. Semiconductor Group 56 Application Guide EPIC(R) and Monitor Channel Programming P STAR = 05 MFFIFO = 1. Byte MFFIFO = 2. Byte STAR = 04 MFTC 1.0 = 00 EPIC FIFO empty, write access enabled Load 1. Byte in FIFO Load 2. Byte in FIFO FIFO not empty, write access enabled Transmit to particular subscriber IOM R transmit-channel address Transmit & receive mode Send 1. FIFO-Byte Wait for ack. Send 2. FIFO-Byte Wait for ack. Send "EOM" STAR = 12 Transfer operating Write 1. Byte to FIFO Transmit ack. Write 2. Byte to FIFO Transmit ack. Set monitor channel inactive Transfer completed FIFO not empty, Read access enabled Read 1. Byte of confirmation Read 2. Byte of confirmation FIFO empty, read access enabled Enable FIFO write access FIFO empty, write access enabled ITD04529 R SBCX MFSAR = XX CMDR = 08 Trans. of 1. Byte Ack. 1. Byte Trans. of 2. Byte Ack. 2. Byte Read 1. Byte Transmit ack. Read 2. Byte Transmit ack. Transmit EOM ack. Send 1. Byte of confirmation Wait for ack. Send 2. Byte of confirmation Wait for ack. Send "EOM" ISTA = 70 STAR = 06 MFFIFO = 1. Byte MFFIFO = 2. Byte STAR = 07 CMDR = 01 STAR = 05 MFFI Figure 38 Monitor Channel Handling with EPIC(R) (all data values hexadecimal) Semiconductor Group 57 Application Guide 3.2.1.3.2 Monitor Procedure "Timeout" (TOD) The SBCX offers an internal reset (monitor procedure "Timeout") for the monitor routine. This reset function transfers the monitor channel into the idle state (MR and MX set to high) by issuing "EOM" (End of Message). Thereby possible lock-up situations will be resolved. It therefore is recommended to enable the internal timeout feature in all systems when no P is capable of detecting and resolving hang-up situations in the monitor procedure (e.g. in a standard NT1). The device checks for lock-up situation every 5 ms. In case a hang-up has been detected "EOM" will be issued on IDP0. Afterwards the original monitor message will be sent in the monitor channel again. The information thus is not lost after a monitor procedure timeout occurred. In applications where a P controls the system this internal reset function may be disabled by programming the TOD bit (timeout disable) in the SM/CI Register to ONE. In this mode no restrictions regarding the time for completing a monitor transfer exists. 3.2.1.3.3 MON-1, MON-2 Commands (S/Q Channel Access) Monitor commands supported by the PEB 2081 divide into three categories. Each category derives its name from the first nibble (4 bits). The first two categories (MON-1 and MON-2) serve a similar function. They are therefore grouped together and will be described in more detail in this section. MON-8 commands are described in the next section. Both MON-1 and MON-2 messages are also referred to as S/Q messages because they are used to read and write the registers containing the information of the S channel (direction NT TE) or the Q channel (direction TE NT) on the S-interface. Via the S-interface S/Q channel it is possible to exchange service or signalling information between the terminal and the network termination/exchange side. The S/Q channel is only available if multiframing was selected in the MFD bit of the MON-8 Configuration register. It is important to note that MON1/2 message provide only access to the device internal S/Q registers. Insertion and extraction of a message on the S-interface is handled automatically by the PEB 2081. Currently no MON-1 and MON-2 commands are defined. The S/Q channel thus operates as a transparent channel only. In the direction NT TE two channels are available. They are named S1 and S2 channel, each of them containing 4 bits of information. In the opposite direction one channel is provided (Q channel, also 4 bit wide). The structure of a MON-1 message is shown below. Table 4 MON-1 Structure 1 Byte 0 0 MON-1 0 1 S1/Q S1/Q S1/Q S1/Q S1 or Q data Semiconductor Group 58 Application Guide The structure of a MON-2 message is similar: Table 5 MON-2 Structure 1 Byte 0 0 MON-2 1 0 S2 S2 S2 S2 S2 data The following table gives an overview of the S/Q messages available: Table 6 MON-1, MON-2 Functions TE DD S1-MON-1 S2-MON-2 Q-MON-1 DU DD S1-MON-1 S2-MON-2 Q-MON-1 LT DU Transmit and Receive in the S1 channel via MON-1 commands Transmit and Receive in the S2 channel via MON-2 command Transmit and receive in the Q channel via MON-1 command Function Non-Auto Mode / Transparent Mode The use of the S/Q channel depends on the S/Q processing mode. The user can choose between the non-auto mode and the transparent mode. These two alternatives are independent of the operational mode the SBCX works in. The non-auto mode is restricted to transfers in the S1 and Q channel. Channel S2 is not available in non-auto mode operation. In non-auto mode a message in the IOM-2 monitor channel is generated only if the Q or S1 data has changed on the S-interface. In transparent mode all three channels, Q, S1, and S2 can be accessed. IOM-2 monitor messages are generated everytime a complete S-interface multiframe has been received (i.e. every 5 ms). The generation of monitor messages thus is completely independent of the received S/Q data. Semiconductor Group 59 Application Guide 3.2.1.3.4 MON-8 Commands (Internal Register Access) The PEB 2081 V 3.4 contains six internal registers. Access to these registers is only possible via the IOM-2 monitor channel. The following registers are implemented in the SBCX V 3.4: q q q q q q Identification Register Configuration Register Loop-back Register IOM-2 Channel Register SM/CI Register MAI Pin Register The identification register is a read only register, all remaining registers are read/write registers. The structure of MON-8 write and read request/response commands are shown in the three tables below: Table 7 MON-8 "Write to Register" Structure 1. Byte 1 0 0 0 r r r r D7 D6 D5 MON-8 Reg. Address 2. Byte D4 D3 D2 D1 D0 Register Data Write In case this function is used in conjunction with multiple P read command (see MAI pin register) a 5 byte long response message will result. Table 8 MON-8 "Read Register Request" Structure 1. Byte 1 0 0 0 0 0 0 0 0 0 0 MON-8 2. Byte 0 r r r r Reg. Address The response issued by the SBCX after having received a "Read Register Request" has the following structure. Table 9 MON-8 "Read Response" Structure 1. Byte 1 0 0 0 r r r r D7 D6 D5 MON-8 Reg. Adr. Confirmation 2. Byte D4 D3 D2 D1 D0 Register Data Read The following sections describe the register features. For bit locations within a register, its initial value after reset and its address please refer to chapter 4. Semiconductor Group 60 Application Guide 3.2.1.3.5 MON-8 Identification Register The contents of the identification register differs with the SBCX version. PEB 2081 V3.3 and 3.4 is identified with the code 42Hex. Former PEB 2081 versions identify themselves with the following codes: PEB 2081 Version A1 ... A3 Version B1, 2.2 Identification 40HEX 41HEX 3.2.1.3.6 MON-8 Configuration Register In the configuration register the user programs the SBCX for different operational modes, selects required S-bus features and controls the function of the MAI interface. The following paragraphs describe the application relevance of all individual configuration register bits. MODE With this bit the user chooses between LT-S and LT-T operational mode. Default selection is LT-S mode. The setting of the MODE bit is only evaluated when pin MODE (No. 15 DIP) is set to ONE. This bit has three different meanings depending on the operational mode of the SBCX: In LT-S and NT modes the S/T bus configuration is programmed. For point-to-point or extended passive bus configurations an adaptive timing recovery must be chosen. This allows the SBCX to adapt to cable length dependent round trip delays. In LT-T mode the user selects the amount of permissible wander before a C/I code warning will be issued by the SBCX. The warning may be sent after 25 s or 50 s. Note: The C/I indication SLIP which will be issued if the specified wander has been exceeded, is only a warning. Data has not been lost at this stage. In TE mode the frequency of the power converter clock at pin X0 (No. 18 DIP) is selected. The user has the choice between a 32 kHz (default) and a 16-kHz signal. Selects the SQ channel handling mode. In non-auto mode operation, the SBCX issues S1 and Q messages in the IOM-2 monitor channel only after a change has been detected. The S2 channel is not available in non-auto mode. In transparent mode monitor messages containing the S1, S2 and Q data are forwarded to IOM-2 once per multiframe (5 ms), regardless of the data content. Programming the SQM bit is only relevant if multiframing on S/T is selected (bit MFD configuration register). See also MON-1 and MON-2 monitor messages. Receive Code Violation Errors. The user has the option to issue a C/I error code (CVR) everytime an illegal code violation has been detected. The implementation is realized according to ANSI T1.605. C/W/P SQM RCVE Semiconductor Group 61 Application Guide LP Loop Transparency. In case analog loop-backs are closed with C/I = ARL or bit SC in the loop-back register, the user may determine with this bit, whether the data is forwarded to the S/T-interface outputs (transparent) or not. The default setting depends on the operational mode. In LT-S and NT by default transparency is selected, for LT-T and TE non-transparency is standard. Finite State Machine Mode. By programming this bit the user has the possibility to exchange the state machines of LT-S and NT, i.e. a SBCX pin strapped for LT-S operates with a NT state machine and vice versa. All other operation mode specific characteristics are retained (MAI interface, etc.). This function is used in intelligent NT configurations where the SBCX needs to be pinstrapped to LT-S mode but the state machine of a NT is desirable. MAI interface Mode. Selects between P interface and I/O mode. The operation of the I/O mode is determined with the MIO bit in the SM/CI register (see MAI interface). Multi-Frame-Disable. Selects whether multiframe generation (LT-S, NT) or synchronization (TE, LT-T) is prohibited or allowed. Enable multiframing if S/Q channel data transfer is desired. When reading this register the bit indicates whether multiframe synchronization has been established or not. FSMM MAIM MFD 3.2.1.3.7 MON-8 Loop-Back Register The loop-back register controls all analog (S/T-interface) and digital (IOM-2 interface) loop-backs. Additionally the wake-up mode can be programmed. AST Asynchronous Timing. Defines the length of the Timing signal (IDP0 = 0) on IOM-2. If synchronous timing is selected the SBCX in NT or LT-S mode will issue the timing request only in the C/I channel of the selected timeslot (C/I = 0000b). This mode is useful for applications where IOM-2 clock signals are not switched off. Here the SBCX can pass the TE initiated activation via C/I = 0000b in IOM-2 cannel 0 upstream to the U-interface device. In case IOM-2 clocks can be turned off during power-down or the LT-S SBCX is pin-strapped to a different timeslot than the U-interface device, synchronous timing signals will not succeed in waking the U-interface device. Under these circumstances asynchronous timing needs to be programmed. Here the line IDP0 is set to ZERO for a period long enough to wake any U-interface device, independent of timeslot or clocks. Typically asynchronous timing is programmed for intelligent NT applications (SBCX pin-strapped to LT-S with NT state machine). Note: The asynchronous timing option is restricted to configurations with the SBCX operating with NT state machine (i.e., LT-S pin-strap & FSMM bit programmed, or NT pin-strap & FSMM bit not programmed). SB1 SB2 Closes the loop-back for B1 channel data close to the activated S/T-interface (i.e., loopback IOM-2 data) in LT-S and NT mode. Closes the loop-back for B2 channel data close to the activated S/T-interface (i.e., loopback IOM-2 data) in LT-S and NT mode. Semiconductor Group 62 Application Guide SC IB1 IB2 IB12 Close complete analog loop-back (2B+D) close to the S/T-interface. Corresponds to C/I = ARL. Transparency is optional. Operational in LT-S and NT mode. Close the loop-back for B1 channel close to the IOM-2 interface (i.e. loop-back S/T data). Transparent. IB1 and IB2 may be closed simultaneously. Close the loop-back for B2 channel close to the IOM-2 interface (i.e. loop-back S/T data). Transparent. IB1 and IB2 may be closed simultaneously. Exchange B1 and B2 channels. IB1 and IB2 need to be programmed. Loops back data received from S/T and interchanges it, i.e. B1 input (S/T) B2 output (S/T) and vice versa. 3.2.1.3.8 MON-8 IOM(R)-2 Channel Register The features accessible via the IOM-2 Channel register allow to implement simple switching functions. These make the SBCX the ideal device for intelligent NT applications. Please refer also to the section "IOM-2 channel switching" later in this application guide. Two types of manipulation are possible: the transfer from the pin-strapped IOM-2 channel (0 ... 7) into IOM-2 channel 0 and a change of the B1, B2 and D data source. B1L B2L DL B1D Transfers the B1 channel from its pin-strapped location into IOM-2 channel 0. Transfers the B2 channel from its pin-strapped location into IOM-2 channel 0. Transfers the D-channel from its pin-strapped location into IOM-2 channel 0. Direction of the B1 channel. Normally pin IDP1 is the data source (input) for all data channels and IDP0 the output. By programming this bit, input and output are interchanged for the B1 data channel, i.e. B1 (IDP0) is input and IDP1 is output. Direction of the B2 channel. Normally pin IDP1 is the data source (input) for all data channels and IDP0 the output. By programming this bit input and output are interchanged for the B2 data channel, i.e. B2 (IDP0) is input and IDP1 is output. C/I Channel handling: Normally the C/I commands are read from the pin-strapped IOM-2 channel. With this bit programmed C/I channel access is only possible via the SM/CI register. D-Channel handling. Selects the protocol for D-channel access. Three alternatives exist: - Transparent D data transmission - D-channel collision resolution according to ITU I.430 - D-channel bus access procedure for intelligent NT applications or configurations involving the "new line card" concept. An entire chapter is dedicated to D-channel access procedures later in this application guide. Details on all three methods including typical applications are described there. B2D CIH DH Semiconductor Group 63 Application Guide 3.2.1.3.9 MON-8 SM/CI Register This multifeature register allows access to the C/I channel, sets the MAI interface mode and controls the monitor time-out and S/G bit function. C/I Allows the user to access the C/I channel if the CIH bit is the IOM-2 register has been previously set. If the CIH bit was not programmed the content of the CI bits will be ignored and the SBCX will access the IOM-2 C/I channel. When reading the SM/CI register these bits will always return the current C/I indication (independent of CIH bit). Time Out Disable. Allows the user to disable the monitor time-out function. Refer to section "Monitor Timeout" earlier in this chapter for details. S/G Enable. This bit is only relevant in TE mode. By programming it, the stop/go bit issued in the IOM-2 channel 2 will also be available at MAI pin No. 5 (pin No. 21, DIP). If this function is required the MAI interface must be programmed for "I/O specific" operation. Maintenance Input Output. Provided bit MAIM was programmed for I/O operation of the MAI interface, bit MIO allows the choice between a standard I/O and I/O specific usage of the MAI interface. Refer to section "Maintenance Auxiliary Interface (MAI)" for details. MAI Pin Register TOD SGE MIO 3.2.1.4 In both I/O specific and standard I/O mode pin levels can be set and read with the MAI pin register. In case the I/O specific mode is implemented, only pins not used for I/O specific purposes may be read or written. In case the P mode is selected (MAIM bit) the MAI pins are redefined as follows to provide a complete P interface. WR Write bit. The user sets the WR bit to low if data needs to be written to a specified address of the P interface. The desired address and data must be written simultaneously with the WR bit into the MAI pin register. Read bit. Allows the user to read data from the specified address of the P interface. Note that a read request must be sent to the SBCX with the "MON-8 Write to Register" structure. The distinction between write and read operation on the P interface is only performed with the WR and RD bits. With bit INT set to ONE an address needs to be specified. With INT set to ZERO all four P addresses are read and returned in a single 5 byte long monitor message. Interrupt. Any change of the level on the INT pin of the P interface will result in the C/I code MAIC to be issued on IOM-2 (for four frames). Additionally the INT bit is used to distinguish between a single address and multiple address reading (see RD bit or MAI interface). Address bits for P interface. RD INT A0, A1 D0, D1, D2 Data bits for P interface. Semiconductor Group 64 Application Guide 3.2.2 S/T-Interface The S-interface establishes a direct link between terminals and the exchange or NT. It consists of two pairs of copper wires: one for the transmit and one for the receive direction. The PEB 2081 inputs and outputs are coupled via matching resistors and transformers to the S-interface. Direct access to the S-interface is not possible. 2B+D user data as well as S/Q channel information can be inserted and extracted via IOM-2 interface. Framing and balancing bits are generated and transmitted automatically by the SBCX. Because chapter 3 is application oriented and the user has no direct access possibility to the S-interface, the following sections give only an overview. For details please refer to the technical description in chapter 4. S/T Frame Structure Transmission over the S-interface is performed at a rate of 192 kbaud. For both directions of transmission a pseudo-ternary code is used. Data is grouped together into S-frames containing 48 bits each, 36 bits contain 2B+D user data (i.e. user data from two IOM-2 frames packed into one S-frame). The remaining 12 bits are reserved for framing, S/Q and service bits. In case multiframing is selected (optional) 20 S-frames are combined to one S-interface multiframe. The start of a new multiframe is marked by a special framing bit (see chapter 4 for details). Figures 39 and 40 illustrate the S-bus framing structure. 1. S-Frame Figure 39 S Multiframe Structure 2 Bit F Figure 40 S-Frame Structure 8 Bit B1 5 Bit F+S+D 2. S-Frame 5 ms 20. S-Frame 8 Bit B2 3 Bit F+D 250 s 8 Bit B1 3 Bit F+D 8 Bit B2 3 Bit F+D Semiconductor Group 65 Application Guide 3.2.3 Maintenance Auxiliary Interface (MAI) The SBCX provides eight pins, MAI (7:0), for maintenance aids and general interface purposes. Two major operational modes are supported: MAI Interface: q I/O Mode q P Mode The I/O mode offers two additional alternatives: q I/O Specific Mode q Standard I/O Mode. To select between these three alternatives the "Configuration" and "SM/CI" registers are programmed. The following table illustrates the register settings: Table 10 Configuration Reg. MAIM 0 0 1 1 SM/CI Register MIO 0 1 0 1 MAI Interface Mode I/O Specific Mode Standard I/O Mode P Mode not applicable The following sections describe the features of the different MAI modes and gives application examples. 3.2.3.1 I/O Specific Mode The I/O specific function mode is selected automatically after a reset. Four pins (MAI 3:0) operate as inputs, four as outputs (MAI 4:7). Depending on the operational mode some of these MAI pins are used to transfer mode specific signals. Pins not required to convey these special signals are used as standard input or output pins. All MAI pins are tristate during RST = `0' or when the SBCX is in the state `reset' unless MAIM is programmed to `1'. After reset all MAI pins are logically `0' and work push/pull. The MAI pins are accessed via the MAI pin register MPR (address 5 H) using the monitor channel. All input pins not allocated to I/O specific functions are monitored continuously. After a change was detected the input values are latched and the C/I indication MAIC will be issued. The input values remain latched until the MAI pin register was read via MON-8 command. I/O specific input pin changes cause no C/I MAIC indication. The pin levels are nevertheless latched correctly everytime a MAIC indication was generated. The following table illustrates the I/O specific pin allocation for all operating modes. Semiconductor Group 66 Application Guide Table 11 I/O Specific MAI Interface LT-S MAI 0 MAI 1 MAI 2 MAI 3 MAI 4 MAI 5 MAI 6 MAI 7 i:NT-STAR i:MPR1 i:MPR2 i:MPR3 o:MPR4 o:MPR5 o:MPR6 o:MPR7 NT i:NT-STAR i:MFD i:TM1 i:TM2 o:MPR4 o:MPR5 o:MPR6 o:MPR7 LT-T i:MPR0 i:CON i:MPR2 i:MPR3 o:MPR4 o:S/G o:MPR6 o:MPR7 TE i:MPR0 i:CON i:MPR2 i:MPR3 o:MPR4 o:S/G o:MPR6 o:MPR7 NT-STAR: In NT or LT-S configurations optionally the NT-STAR mode may be used (see sections 2.1.3 and 2.1.6). In these configurations the IOM-2 bus is operated at a DCL rate of 512 kHz. All SBCX thus write onto the same IOM-2 channel. Because their outputs are logically ANDed "0"s win on the bus. In the opposite direction all SBCXs receive identical information from the controller. If an activation attempt is initiated from the upstream controller, the activation normally (i.e. without NT-STAR mode) can only be completed successfully when all terminals are connected. In case a single terminal was not connected the corresponding NT/LT-S SBCX would stop the activation process in the state "G2 pend. act." because no INFO3 is received. In this state the C/I indication AR, binary code 1000b, is issued. The 3rd ZERO would overwrite the AI indications, binary code 1100b, from the remaining, correctly activated, SBCXs. Programming the NT-STAR mode by setting this pin to ZERO avoids this conflict. A NTSTAR configuration can therefore be correctly activated even if not all terminals are connected. Furthermore, transitions from the states "wait for AID" or "G3 activated" to "lost framing on S" under the condition of not receiving INFO3 is disabled. MFD: Multi Frame Disable In NT mode the transmission of the 5 ms multiframe signalling bits is disabled (M and S bits high) with a HIGH at this pin. A LOW level enables the multiframe generation provided the MFD bit in the configuration register was not programmed to disable it. The pin strapping has higher priority than the register setting. CON: This input pin can be used to prevent a TE/LT-T from initiating an activation under emergency conditions. For this purpose it must be connected to a signal indicating the reverse polarity of a phantom power supply (e.g. pin EME of the PSB 2120). Semiconductor Group 67 Application Guide A LOW level at this input (D-channel collision must be programmed via DH bit in IOM channel register) prevents transmission of INFO1 after AR (activation-request) has been received on the C/I channel. An activation initiated by the network side (reception of INFO2/INFO4) is possible independently of the CON pin level. In LT-T mode bit DH in the IOM-2-Channel register must be set to "1" to enable the CON pin functionality. TM1: Test Mode 1 A LOW at this input transfers the NT SBCX into test mode 1. In this test mode pseudoternary pulses are transmitted at a rate of 2 kHz. Test Mode 2 A LOW at this input transfers the NT SBCX into test mode 2. In this test mode pseudoternary pulses are transmitted at a rate of 96 kHz. Stop/Go This pin can be used to inform the D-channel controller in TEs and LT-Ts when the S-bus D-channel is occupied by another S-interface device (see section 2.1.7). LT-T mode: In LT-T mode this feature is only available after setting the DH bit in the IOM-2 register to ONE. In case the S-interface D-channel is busy, the S/G pin is set to ZERO. This must be interpreted by the D-channel controller (e.g. IDEC) as a "stop D-channel transmission" indication. In LT-T mode the S/G bit is set synchronously to the D-channel, i.e. the stop/go information is transmitted in the same time-slot as the corresponding SBCX is pinstrapped to. This mechanism allows the D-channel controller to distinguish between up to eight SBCX S/G pins (S/G = `0' means `stop', S/G = `1' means `go'). In mixed configurations with LT-T and LT-S mode devices connected together at pin MAI5, these MAI5 outputs have to be decoupled by using diodes. Otherwise the asynchronous push/pull outputs of the LT-S mode devices could disturb the synchronous (D-channel oriented) outputs of the LT-T mode devices. TE mode: In TE mode this feature is only available after setting the SGE bit in the SM/CI register to HIGH. In both operational modes the D and E bits on the S-interface are monitored continuously to issue always the correct S/G status. Requires the same pull-up resistor as IDP0. In TE mode the S/G pin has the same polarity as the S/G-bit on IOM-2. S/G = `1' stands for `stop' and S/G = `0' means `go'. As opposed to the LT-T mode pin S/G keeps its value between the D-channel time-slots on IOM-2. TM2: S/G: Applications I/O specific MAI pins are under control of the SBCX. The user therefore can only influence the standard I/O pins. Examples demonstrating the use of standard I/O pins are presented in the following section. Semiconductor Group 68 Application Guide 3.2.3.2 Standard I/O Mode In standard I/O mode no pins are reserved for special signals. Thus four input and four output lines are available to the user for general purpose interface applications. Do not use this mode however when in need of special features like STAR operation, collision detection in LT-T/TE point-multipoint configurations etc. MAI0 and MAI3 are used for inputs. A change at any input pin will cause a MAIC C/I indication to be issued and the data to be latched. Data will remain latched until read out from the MAI pin register with a MON-8 command. MAI4 and MAI7 serve as outputs. The pin level is determined by the corresponding bit level in the MAI pin register. The value specified for the lower four bits (inputs) does not matter. Application The following example illustrates the use of the standard I/O MAI interface. The same procedures apply to the I/O specific MAI mode for all pins not reserved for special signals. IOM(R)-2 MON-8 Config: MAIM = 0 MON-8 SM/CI: MIO = 1 MON-8 MAI: (8100H) (8301H) (85F0H) SBCX - - MAI4 = (1) MAI5 = (1) MAI6 = (1) MAI7 = (1) (1) = MAI0 (0) = MAI1 (1) = MAI2 (0) = MAI3 ; Set all outputs to HIGH ; Select standard I/O C/I MAIC: (0101) ; Change input levels MON-8 MAI: MON-8 MAI: (8005H) (85X5H) ; Read MAI register request ; Return value MAI inputs Semiconductor Group 69 Application Guide 3.2.3.3 P MAI Mode The interface structure is adapted to the register structure of the IEPC. It consists of three data bits MAI0 ... 2, two address bits MAI4,5, read and write signals MAI6 and MAI7 respectively as well as an interrupt facility MAI3. The address bits are latched, they may therefore in general interface applications be used as output lines. For general interface inputs each of the three data bits is suitable. Read and write operations are performed via MON-8 commands. Three inputs and two outputs are thus available to connect external circuitry. The interrupt pin is edge sensitive. Each change of level at the pin MAI3 will initiate a C/I code "MAIC" (0101) lasting for four IOM frames. Interpretation of the interrupt cause and resultant actions need to be performed by the control unit. Usage of the P interface differs from the standard I/O or I/O specific interface. As for these two interface types the P interface makes use of the MAI pin register. However only MON-8 commands with the "write to register" structure may be used. The "read register request" structure is not interpreted if the MAI pin register is accessed in combination with the P mode. The differentiation between a P interface write operation and a P interface read operation is performed only by activating either the RD or the WR bits within the MAI pin register. In both cases the "write to register" structure is used. Depending on the INT bit specified together with a read P interface request either the data from a single, specified address is read (INT = ONE) or all addresses are read (INT = ZERO). In case only a single address is to be read, the SBCX returns the value in a 2-byte MON-8 message (structure: 85H, MAI pin register). If all four addresses were read the response is a single 5 byte long (85H, MAI Reg. (Adr0), ... , MAI Reg. (Adr. 3)) MON-8 monitor message. In this function the data from the following address will be read from the P interface as soon as the previous MON-8 byte has been acknowledged on the IOM-2 bus by the controller. Application The following three examples illustrate a write operation as well as a single address and full address read operation. It is assumed that no power controller is connected. The data lines are clamped to the values specified in the examples, the address lines are unconnected. 1. Write to P Interface: IOM(R)-2 MON-8 Config: MAIM MON-8 MAI: (8140H) (855EH) SBCX - MAI4 pin = (1) MAI5 pin = (0) MAI2 pin = (1) MAI1 pin = (1) MAI0 pin = (0) ; Program P interface ; Activate WR signal, set ; address 1 (latched) ; Set data to value 6 ; (non-latched) Semiconductor Group 70 Application Guide 2. Read from P Interface (single address): IOM(R)-2 SBCX MAI2 pin = (1) MAI1 pin = (0) MAI0 pin = (1) MON-8 Config: MAIM MON-8 MAI: (8140H) (85B8H) MAI5 pin = (1) MAI4 pin = (1) MON-8 MAI: (85BDH) - ; Constant values on ; data lines ; Program P interface ; Activate RD, INT = (1) ; read from address 3 ; 2 byte response incl. ; data lines from adr. 3 3. Read from P Interface (complete address scan): The following example assumes that a device capable of decoding addresses is connected to the P interface. The data values to be returned from the addresses are: Adr. 0: Adr. 1: Adr. 2: Adr. 3: Data = 7 Data = 6 Data = 5 Data = 4 IOM(R)-2 MON-8 Config: MAIM MON-8 MAI: MON-8 MAI: (8140H) (8580H) (85 87 96 A5 B4H) SBCX - ; Program P interface ; Set INT = (0), activate RD ; read all addresses ; 5 byte response incl. ; data from adr. 0 ... 3 Semiconductor Group 71 Application Guide 3.3 Control Procedures Control procedures describe the commands and messages required to control the PEB 2081 in different modes and situations. This chapter shows the user how to activate and deactivate the device under various circumstances. In order to keep this chapter as application oriented as possible only actions and reactions the user needs to initiate or may observe are mentioned. Technical details on transmitted status bits and signals are described in chapter 4 of this manual. For transfer of the C/I commands to and from the ICC or EPIC proceed as described in section 3.2.1.2. 3.3.1 Activation Initiated by Exchange (LT-S) TE/LT-T IOM(R)-2 3.3.2 C/I C/I C/I C/I C/I C/I DC DI RSY AR AI AR8/AR10 (1111b) (1111b) (0100b) (1000b) (1100b) (1000b/1001b) LT-S IOM(R)-2 C/I C/I C/I C/I C/I DC (1111b) DI (1111b) ; Initial state is G1 deactivated ; and F3 Power Down (c) ; Activation completed ; Start activation AR (1000b) AR (1000) AI (1100) Activation Initiated by Exchange (NT) In case the counter station of the TE of LT-T is in NT mode the C/I "AI" command needs to be issued at the end. The first section of the activation procedure is identical to the activation with SBCX in LT-S mode. TE/LT-T IOM(R)-2 C/I C/I C/I C/I C/I C/I DC DI RSY AR AI AR8/AR10 (1111b) (1111b) (0100b) (1000b) (1100b) (1000b/1001b) NT IOM(R)-2 C/I C/I C/I C/I C/I C/I DC DI AR AR AI AI (1111b) (1111b) (1000b) (1000) (1100) (1100) (c) ; Initial state is G1 ; Deactivated and F3 ; Power Down ; Activation starts (c) ; Transfer to G3 Activated Semiconductor Group 72 Application Guide 3.3.3 Activation Initiated by Terminal (TE/LT-T) The following scheme illustrates how a terminal initiates an activation. As described in the previous section the command C/I "AI" needs to be sent at the end if the device is operating in NT mode. TE/LT-T IOM(R)-2 (c) (c) (c) C/I C/I C/I 1) LT-S (NT) IOM(R)-2 C/I C/I DC DI (1111b) (1111b) ; Initial state is G1 Deactivated ; and F3 Power Down ; Request timing (IOM clocks) DC DI TIM PU AR8 (1111b) (1111b) (0000b) (0111b) (1000b) C/I C/I TIM Release 2) C/I C/I C/I RSY AR AI (0100b) (1000b) (1100b) C/I C/I AR AI (1000b) (1100b) (1100b) ; Start Activation ; Transfer to G3 Activated ; ; ; Transfer to G3 Activated ; in NT mode) (C/I AI Notes: 1) For PEB 2070 TIM is requested with register SPCR = 80H 2) For PEB 2070 TIM is released with register SPCR = 00H 3.3.4 Deactivation A deactivation of the S-interface can only be initiated by the exchange side (SBCX in NT or LT-S mode). It is possible to begin a deactivation process from all interim activation states, i.e. not only from the fully activated state. The following example nevertheless assumes that the line is fully activated when the deactivation is initialized. TE/LT-T IOM(R)-2 (c) C/I C/I C/I C/I AI8 DR DI DC (1100b) (0000b) (1111b) (1111b) NT/LT-S IOM(R)-2 C/I C/I C/I C/I C/I AI DR TIM DI DC (1100b) (0000b) (0000b) (1111b) (1111b) (c) (c) ; Initial state ; start deactivation ; ; "G1 Deactivated" ; Transfer to "F3 Power Down" Semiconductor Group 73 Application Guide 3.3.5 D-Channel Access Control D-channel access control was defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. Figure 41 illustrates that collisions are possible on the TIC- and the S-bus. ICC ICC ICC U SBCX TE1 SBCX NT IEC-Q NT ICC SBCX TE 2 ICC SBCX TE 8 TIC Bus S Bus ITS05113 Figure 41 D-Channel Access Control on TIC Bus and S Bus The TIC bus is used to control D-channel access on the IOM interface when more than one HDLC controller is connected. This configuration is illustrated in the above figure for TE1 where three ICCs are connected to one IOM-2 bus. On the S bus the D-channel control is handled according to the ITU recommendation I.430. This control mechanism is required everytime a point to multipoint configuration is implemented (NT TE1 ... TE8). While the S-bus collision detection is handled by the SBCX itself, TIC bus access is mainly controlled by the HDLC controller (e.g. ICC). The following sections describe both control mechanisms because the TIC bus, although largely handled by the HDLC controller, represents an important part of D-channel access. Semiconductor Group 74 Application Guide 3.3.5.1 TIC Bus D-Channel Control in TE The TIC bus was defined to organize D- and C/I channel access when two or more D- and C/I channel controllers can access the same IOM-2 timeslot. Bus access is controlled by five bits in IOM-2 channel No. 2 (see section 3.2.1.1): Upstream: Downstream: BAC TBA0 ... 2 S/G Bus access control bit TIC bus address bits 0 ... 2 Stop/Go bit When a controller wants to write to the D or C/I channel the following procedure is executed: 1. Controller checks whether BAC bit is set to ONE. If this is not the case access currently is not allowed: the controller has to postpone transmission. Only if BAC = 1 the controller may continue with the access procedure. 2. The controller transmits its TIC bus address (TBA0...2). This is done in the same frame in which BAC = "1" was recognized. On the TIC bus binary "ZERO"s overwrite binary "ONE"s. Thus low TIC bus addresses have higher priority. 3. After transmitting a TIC bus address bit, the value is read back (with the falling edge) to check whether its own address has been overwritten by a controller with higher priority. This procedure will continue until all three address bits are sent and confirmed. In case a bit is overwritten by an external controller with higher priority, the controller asking for bus access has to withdraw immediately from the bus by setting all TIC bus address bits to ONE. 4. If access was granted, the controller will put the D-channel data onto the IOM-2 bus in the following frame provided by the S/G bit is set to ZERO (i.e. S-bus free to transmit). The BAC bit will be set to ZERO by the controller to block all remaining controllers. In case the S/G bit is ONE this prevents only the D-channel data to be switched through to the IOM-2 bus. The TIC bus request remains unaffected (i.e. if access was granted the TIC address and BAC bit are activated). As soon as the S-bus D-channel is clear and the S/G bit was set back to "GO" the controller will commence with data transmission. The S/G Bit generation in IOM-2 channel 2 is handled automatically by the SBCX operating in TE mode. Additionally the Stop/Go information may be issued at the MAI5 pin by setting the SGE bit in the SM/CI register to ONE. 5. After the transmission of an HDLC frame has been completed the ICC controller withdraws from the TIC bus for one IOM-2 frame. This also applies when a new HDLC frame is to be transmitted in immediate succession. With this mechanism it is ensured that all connected controls receive an equally fair chance to access the TIC bus. Semiconductor Group 75 Application Guide 3.3.5.2 S-Bus Priority Mechanism for D-Channel The S-bus access procedure specified in ITU I.430 was defined to organize D-channel access with multiple TEs connected to a single S-bus. To implement collision detection the D (channel) and E (echo) bits are used. The D-channel S-bus condition is indicated towards the IOM-2 interface with the S/G bit (see previous section). The access to the D-channel is controlled by a priority mechanism which ensures that to all competing TEs is given a fair access chance. This priority mechanism discriminates among the kind of information exchanged and information exchange history: Layer-2 frames are transmitted in such a way that signalling information is given priority (priority class 1) over all other types of information exchange (priority class 2). Furthermore, once a TE having successfully completed the transmission of a frame, it is assigned a lower level of priority of that class. The TE is given back its normal level within a priority class when all TEs have had an opportunity to transmit information at the normal level of that priority class. The priority mechanism is based on a rather simple method: A TE not transmitting layer-2 frames sends binary 1s on the D-channel. As layer-2 frames are delimited by flags consisting of the binary pattern "01111110" and zero bit insertion is used to prevent flag imitation, the D-channel may be considered idle if more than seven consecutive 1s are detected on the D-channel. Hence by monitoring the D echo channel, the TE may determine if the D-channel is currently used by another TE or not. A TE may start transmission of a layer-2 frame first when a certain number of consecutive 1s has been received on the echo channel. This number is fixed to 8 in priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and 11 for class 2. A TE, when in the active condition, is monitoring the D echo channel, counting the number of consecutive binary 1s. If a 0 bit is detected, the TE restarts counting the number of consecutive binary 1s. If the required number of 1s according to the actual level of priority has been detected, the TE may start transmission of an HDLC frame. If a collision occurs, the TE immediately shall cease transmission, return to the D-channel monitoring state, and send 1s over the D-channel. 3.3.5.3 S-Bus D-Channel Control in TEs The SBCX in TE mode continuously compares the D data bits with the received E-echo bits. Depending on the priority class selected, 8 or 10 consecutive ONEs need to be detected before setting the S/G bit to ZERO. With bit SGE in the SM/CI register the S/G bit may optionally be issued on pin MAI5. The priority class (priority 8 or priority 10) is selected by transferring the appropriate activation command via the Command/Indication (C/I) channel of the IOM-2 interface to the SBCX. If the activation is initiated by a TE, the priority class is selected implicitly by the choice of the activation command. If the S-interface is activated from the NT, an activation command selecting the desired priority class should be programmed at the TE on reception of the activation indication (AI8). In the activated state the priority class may be changed whenever required by simply programming the desired activation request command (AR8 or AR10). Semiconductor Group 76 Application Guide Application 1. Priority Class 8/10 Selection with NT Initiated Activation TE IOM(R)-2 (c) (c) C/I C/I C/I C/I C/I C/I C/I C/I DC DI RSY AR AI AR8 (1111b) (1111b) (0100b) (1000b) (1100b) (1000b) LT-S (NT) IOM(R)-2 C/I C/I C/I C/I C/I C/I DC DI AR AR AI AI (1111b) (1111b) (1000b) (1000b) (1100b) (1100b) (c) (c) ; Request timing (IOM clocks) ; Activation with second C/I C/I C/I C/I AR AR AI AI (1000b) (1000b) (1100b) (1100b) (c) ; ; Allocate highest priority (c) ; priority (e.g. for packet data) ; Start activation from ; NT side ; ; Allocate highest priority ; (e.g. for signaling data) ; Allocate lower priority ; for packet data D: transfer HDLC frame AR10 (1001b) AI10 (1101b) D: transfer packet data 2. Priority Class 8/10 Selection with TE Initiated Activation TE IOM(R)-2 (c) (c) (c) (c) C/I C/I C/I C/I C/I C/I C/I C/I C/I C/I C/I DC DI TIM1) PU (1111b) (1111b) (0000b) (0111b) 2) NT IOM(R)-2 C/I C/I DC DI (1111b) (1111b) AR10 (1001b) TIM Release RSY AR AI10 AR8 AI8 (0100b) (1000b) (1101b) (1000b) (1100b) D: transfer packet data D: transfer HDLC frame Note: 1) For PEB 2070 TIM is requested with register SPCR = 80H 2) For PEB 2070 TIM is released with register SPCR = 00H Semiconductor Group 77 Application Guide 3.3.5.4 S-Bus D-Channel Control in LT-T In LT-T mode the SBCX is primarily considered to be in a point-to-point configuration. In these configurations no S-bus D-channel collision can occur, therefore the default setting after resetting the SBCX is transparent (IOM-2 S-bus) D-channel transmission. In case a point to multipoint configuration is implemented D-channel collision resolution according to ITU I.430 needs to be programmed in the "IOM channel register" [bit DH set to ONE]. In this mode the SBCX will issue a strobe signal at pin MAI5 (S/G bit) to control the LAPD controller IDEC. This strobe signal is issued synchronously to the D-channel, i.e. in case more SBCXs operate in different IOM-2 channels (selection with pin strapping) each SBCX sends its S/G signal in its own IOM-2 channel. This allows the IDEC to distinguish between multiple S/G signals on a single S/G control line (see section 2.1.7). Priority allocation is identical to that described for the TE mode. For application example refer also to the last section [DH bit must be set in addition]. 3.3.5.5 D-Channel Control in the Intelligent NT (TIC-and S-Bus) In intelligent NT applications both the SBCX and one or more D-channel controllers have to share a single upstream D-channel. For this purpose the SBCX must be programmed in the IOM channel register to perform a partial TIC bus evaluation [DH = "1"]. The intelligent NT configuration involves a layer-1 device (IBC, ISAC-P TE, IEC-Q) operating in TE mode (1.536 MHz DCL rate), one or more D-channel controllers and a SBCX in LT-S mode (Dchannel transmitting in IOM-2 channel 0). With the DH bit set to ONE, the SBCX V 3.4 in LT-S mode interprets the A/B, BAC bit and monitors the S-bus D-channel activity. Both S/G and BAC bit, the S-bus echo channel and the upstream IOM-2 D-channel data are controlled by these inputs according to the following procedure: 1. NT D-Channel Controller Transmits Upstream In the initial state neither the intelligent NT D-channel controller nor any of the terminals connected to the S-bus transmit in the D-channel. The exchange indicates via the A/B bit (controlled by layer 1) that D-channel transmission on this line currently is permitted (A/B = "1"). Data transmission could temporarily be prohibited by the exchange when only a single D-channel controller handles more lines (A/B = "0", ELIC-concept). The SBCX thus receives A/B = "1", BAC = "1" and transmits S/G = "0". The access will then be established according to the following procedure: q D-channel controller verifies that BAC bit is set to ONE. q D-channel controller issues TIC bus address and verifies that no controller with higher priority requests transmission. q D-channel controller issues BAC = "0". q SBCX reacts to BAC="0" by transmitting the S/G bit with inverse polarity of the A/B bit S/G = "0"= A/B. q SBCX transmits inverted echo channel (E bits) on the S-bus to block all connected S-bus terminals (E = D). q D-channel controller commences with D data transmission on IOM-2 as soon as it receives S/G = "0". Semiconductor Group 78 Application Guide q After D-channel data transmission is completed the controller sets the BAC bit to ONE. q SBCX pulls S/G bit to ZERO. q SBCX transmits non-inverted echo (E = D). 1) Note: 1. Although the D-channel controller releases the TIC bus for one IOM-2 frame even if a new HDLC frame needs to be transmitted in immediate succession, this one frame period is not sufficient to allow a S-bus terminal to request the D-channel successfully. The reason is that at least 8 ONEs need to be recognized by a terminal in the echo-channel before it can start with D-channel transmission (in the meantime the intelligent NT D-channel controller would have aquired D-channel transmit permission again). To ensure equal access chances for the S-bus terminals, the intelligent NT controller software must delay any new TIC bus access request for at least 5 IOM-2 frames. Figure 42 illustrates the signal flow in an intelligent NT and the algorithm implemented in the SBCX. 2. Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: q SBCX (in intelligent NT) recognizes that the D-channel on the S-bus is active. q SBCX sets S/G = 1 to block NT D-channel controller q SBCX transfers S-bus D-channel data transparently through to the upstream IOM-2 bus (IOM-2 channel 0). q After D-channel transmission has been completed by the terminal and the SBCX in the intelligent NT recognizes the idle condition on the S-bus D-channel, the S/G bit is set to ZERO. In case the exchange prohibits D data transmission on this line the A/B bit is set to ZERO (block). This forces the intelligent NT SBCX to transmit an inverted echo channel on the S-bus, thus disabling all terminal requests, and switches S/G to A/B, which blocks the HDLC controller in the intelligent NT. Note: 1. Although the SBCX operates in LT-S mode and is pinstrapped to IOM-2 channel 0 or 1 it will write into IOM-2 channel 2 at the S/G bit position. Semiconductor Group 79 Application Guide Exchange IOM R -2 Master Device (TE Mode 1.536 MHz) A/B DD DU A/B S/G D D BAC SBCX (LT-S) D Channel E Channel S/G DD ICC BAC ACT & BAC Reset A/B = 0 External Access E=D S/G = A/B BAC & D-Idle Idle E=D S/G = 0 D-Idle SBCX Access D-Idle E=D S/G = 1 ITS05115 Figure 42 Data Flow for Collision Resolution Procedure in Intelligent NT The SBCX uses the Echo-bit of the S-interface to control the transfer of D-channel information from the terminals at the S-interface. It also controls the state of the Stop/Go bit (S/G) and evaluates the A/B bit. The state machine for D-channel access uses three states: External access The D-channel is occupied by another source indicated by the BAC-bit (BAC=0). The S/G bit corresponds to the invers of the A/B bit. The Echo-bits are set to `D'. The D-channel is transparent and no other device occupies the D-channel (BAC=1). The S/G bit is set to `0'. The Echo-bits correspond to the received D-bits of the S-interface. The D-channel is transparent and occupied by the SBCX. The S/G bit is set to `1'. Idle SBCX Access `D-Idle' is `1' if the received D-channel information from the S/T interface is idle (8 x `1'). `D-Idle' changes to `0' after a `0' bit has been received from the S-interface D-channel. `ACT' is set to `1' if the S-interface is in the activated state. Semiconductor Group 80 Application Guide 3.3.6 IOM(R)-2 Interface Channel Switching In order to realize intelligent NT configurations the SBCX provides basic switching functions. These include: q Individual channel transfer from IOM-2 channel 1 to IOM-2 channel 0. q Individual channel reversion on input and output lines. All switching functions are controlled via the MON-8 "IOM-2 channel" register (see MON-8 description). The following sections illustrate a variety of possible switching combinations typical for the intelligent NT. To facilitate the description of the switching function figure 43 illustrates a typical intelligent NT with the speech CODEC ARCOFI combined with several terminals. Monitor programming for both ARCOFI and SBCX can only be performed in monitor channel 1. ICC LT-S Mode Channel 1 IDP0 ARCOFI R TE1 IOM R -2 (1.536 MHz) TE Mode Channel 0 DIN IEC-Q DOUT Exchange ISAC -S R SBCX IDP1 DU TE8 DD R ARCOFI R ARCOFI R ISAC -S Channel 1 UTE ITS05114 Figure 43 Intelligent NT-Configuration for IOM(R)-2 Channel Switching Semiconductor Group 81 Application Guide The following four examples illustrate typical switching operations. Three of them are programmed in the "IOM-2 Channel" register, example No. 4 makes use of the "Loop-back" register. All register bits related to the B1 or B2 channel are set to ZERO unless otherwise stated. 1. Connection B1 (e.g. TE1) Exchange, B2 (e.g. TE8) Exchange SBCX IDP0 B1L = 1 IDP1 B1 B2 DIN B2L = 1 IOM R -2 Reg. B1 B2 DOUT DU R DD ARCOFI Power-Down ITS05116 2. Connection B1 (e.g. TE1) Exchange, B2 (e.g. TE8) U-TE SBCX IDP0 B1L = 1 IDP1 IC2 B1 IOM R -2 Reg. IC2 D OUT B1 D IN B2D = 1 DU R DD ARCOFI Voice Data to IC2 ITS05117 Semiconductor Group 82 Application Guide 3. Connection U-TE (B1) Exchange, B2 (e.g. TE1) Exchange SBCX IDP0 B2L = 1 IDP1 IOM R -2 Reg. B1 B2 B1 DOUT B2 DIN DU R DD ARCOFI Voice Data to B1 ITS05118 4. Connection TE1 (B1) TE8 (B2), U-TE (B1 or B2) Exchange SBCX IDP 0 IB1= 1 IB2 = 1 IB12 = 1 B1 B2 B2 B1 D IN B2 or B1 B2 or B1 Loopback Reg. D OUT IDP1 DU R DD ARCOFI Voice Data to B1 or B2 ITS05119 Semiconductor Group 83 Application Guide 3.4 Maintenance Functions This chapter summarizes all features provided by the SBCX V 3.4 to support system maintenance and system measurements. Two main groups may be distinguished: - maintenance function to close and open test loop-backs. - test modes required for system measurements. The next sections describe these maintenance functions and their applications. 3.4.1 Test Loop-Backs Test loop-backs are specified by national PTTs in order to facilitate the location of defect systems. Each position of defined (ITU I.430 Appendix I) loop-backs is illustrated in figure 44. SBCX A 1) S 4 SBCX IOM B1 2,3 2) R IEC-Q U IEC-Q B2 ,C 3) SBCX TE or LT-T NT1/NT2 S Exchange ITS05120 Figure 44 Test Loop-Backs Supported by PEB 2081 Notes: 1. In previous data sheets for the PEB 2081 ITU loop-back A was referred to as loop-back 3. 2. Loop-back 2 is closed in a NT1, loop-back 3 is closed in a NT2. 3. Loop-back C is closed in a NT1, loop-back B 2 is closed in a NT2. Loop-back 2 is controlled by the exchange. Loop-back 4 may be under exchange or local control. Loop-backs A, B1, B2, C are initiated by the terminal or the NT2. Loop-back 3 is started by the NT2. All loop-backs may be either transparent or non-transparent. Loops are closed in the SBCX with C/I commands or MON-8 register access [loop-back register]. The following sections describe the implementation of these loops in detail. Semiconductor Group 84 Application Guide 3.4.1.1 Complete Loop-Backs (No. 2, No. 3, and No. A) Internal Loop-Backs In a complete loop, all three channels (B1, B2 and D) are looped back at the S/T-interface. In a "transparent loop" the data are also sent forward (in addition to being looped back), whereas in a "non-transparent loop" the forward data path is blocked (ITU I.430). Loop A is activated with C/I channel command Activate Request Loop (ARL). An S/T-interface is not required since INFO3 is looped back to the receiver internally. When the receiver has synchronized itself to this signal, the message "Activate Indication Loop" (AIL) is delivered in the C/I channel. No signal (INFO0) is transmitted over the S/T-interface. If, during loop A, an incoming signal is detected on the line, this is indicated by the message "Resynchronization" (RSY), although the loop is maintained. It is in the responsibility of layer-2 control to release loop A. Loop 2 and Loop 3 is similarly activated over the IOM-2 interface with Activate Request Loop (ARL). No S/T line is required. INFO4 is looped back to the receiver and also sent to the S/T-interface. When the receiver is synchronized, the message "AI" is sent in the C/I channel. Setting the LP-bit in the configuration register to ONE will make loop 2,3 non-transparent. While loop-back A is closed unconditionally (i.e. loop-back A may be started from any state in TE or LT-T mode), loop-backs 2 and 3 may be initiated from three (LT-S) resp. four (NT) states (see state machine NT and LT-S mode in chapter 4). The following examples demonstrate the use of loop-backs A, 2 and 3. 1. Loop-Back A (TE or LT-T) TE/LT-T IOM-2 (c) ( C/I Any state XX C/I C/I C/I C/I ARL ARL AIL RSY (XXXXb) (1010b) (1010b) (1110b) (0100b) ; Loop-back closed successfully ; Incoming signal detected) ; Unconditional command ; Close loop-back A 2. Loop-Back 2, 3 Transparent (NT1 or NT2) LT-S/NT IOM(R)-2 C/I C/I C/I C/I C/I DC DI ARL AR AI (1111b) (1111b) (1010b) (1000b) (1100b) ; Loop-back closed successfully ; Close loop-back 2, 3 ; Initial state is "G1 deactivated" Semiconductor Group 85 Application Guide External Loop-Backs In order to enable complete systems diagnostics (including transformers etc.) it is possible to close an external loop at the four wire S/T-interface. In that case the signal transmitted onto the line is fed to the receiver. SX 1 33 2 :1 100 SX 2 33 PEB 2081 SBCX SR 1 10 k 2 :1 100 ITS04016 SR 2 10 k Figure 45 External Loop at the S/T-Interface In NT/LT-S mode the SBCX is ready to run in this configuration by performing a normal activation. In TE/LT-T mode the LP-bit (configuration register) has to be set to one and then the loop has to be activated using the "ARL" command. The C/I sequence occurring at the IOM-2 interface will correspond to that of the activation of loop A. The SBCX is in the state `loop A activated' and transmits the indication RSY instead of AIL. Semiconductor Group 86 Application Guide 3.4.1.2 Single Channel Loop-Backs (No. 4, No. B1/2, No. C) With the S/T-interface being in the activated state single channel loops are possible for the B channels in all directions, i.e. from the S/T-interface to the IOM-2 interface and back or vice versa. They are involved by setting the according bit in the Loop-back Register. Please note, that setting the SC-bit has the same effect as closing loops No. 2 or 3 respectively with the equivalent C/I command. IOM R -2 Interface TE/LT-T S/T Interface NT/LT-S INFO4 Set Bit: IB1 IB2 IB12 Set Bit: SB 1 SB 2 SC INFO3 B1, B2 B1, B2 Set Bit: IB1 IB 2 IB12 IOM R -2 Interface B1, B2 ITS04015 Figure 46 Single Loops of the SBCX Semiconductor Group 87 Application Guide 3.4.2 Monitoring of Illegal Code Violations The SBCX V 3.4 offers the option of monitoring the S-bus for illegal code violations. If bit RCVE in the configuration register is set to ONE a Far End Code Violation (FECV) function according to ANSI T1.605 is implemented. This feature is available independently of multiframing on the S/Tinterface. 3.4.3 Test Modes and System Measurements The SBCX V 3.4 supports system measurements with two special test modes. In the next section these modes are described in detail. The sections following the test mode description present an overview over the most important system measurements. 3.4.3.1 Test Mode 1 In test mode 1 the SBCX issues alternating pulses at a frequency of 2 kHz. In other S-interface devices this mode is also referred to as "Send Single Zeros". Test mode 1 (TM1) may be used in all operational modes supported by the SBCX. This mode is selected with a C/I command: - software selection: C/I = TM1 (0010b) In case the SBCX is operated in TE or LT-T mode the device will return the same binary C/I code after the test mode has been started successfully. In NT or LT-S mode the C/I indication "TIM" is issued from the "Test Mode" state. 3.4.3.2 Test Mode 2 In Test Mode 2 (TM2) the SBCX issues alternating pseudo-ternary pulses at a frequency of 96 kHz. In other S-interface devices this mode is also referred to as "Send Continuous Zeros". Test mode 2 may be used in all operational modes supported by the SBCX. This mode is selected with a C/I command: - software selection: C/I = TM1 (0011b) In case the SBCX is operated in TE or LT-T mode the device will return the same binary C/I code after the test mode has been started successfully. In NT or LT-S mode the C/I indication "TIM" is issued from the "Test Mode" state. Semiconductor Group 88 Application Guide 3.4.3.3 Pulse Mask Measurement q Pulse Mask defined in ITU I.430 section 8.5.3 q S-interface is terminated with: - 50 (TE and NT equipment) - 400 (TE equipment only) - 5.6 (TE equipment only) q B-channel loop is neccessary IB1, IB2 in Loopback Register or Loop in switching unit q Measurement performed with oscilloscope or Siemens K1403 q Possible problems: - 50 test not successful modify transmitter resistors on S/T-interface circuitry - 400 test shows undershoot minimize capacitances in the external circuitry 3.4.3.4 NT Transmitter Output/Receiver Input Impedance q Impedance Templates defined in ITU I.430 sections 8.5.1.1 and 8.6.1.2 q Output impedance measurement: q q q q - inactive or transmission of binary ONEs. Applies sinusoidal voltage of 100 mVrms. Requirement: template - transmission of binary ZEROs. Requirement: 20 - 50 S-interface termination - 400 S-interface termination Input impedance measurement: - Applied sinusoidal voltage of 100 mVrms. Requirement: template - Applied 96 kHz frequency with 1.2 V peak value. Requirement: current 0.6 mA SBCX is in "deactive" state when transmission of binary ONEs is required and in TM1 when transmission of binary ZEROs is required. Measurement performed with impedance analyzer or Siemens K1403 Possible problems: Not known. TE Transmitter Output/Receiver Input Impedance 3.4.3.5 q Impedance templates defined in ITU I.430 sections 8.5.1.2 and 8.6.1.1. q Input and output measurements are identical: - inactive and power-down or transmission of binary ONEs. Applied sinusoidal voltage of 100 mVrms. Requirement: template. - inactive and power-down or transmission of binary ONEs. Applied 96-kHz frequency with 1.2 V peak value. Requirement: Current 0.6 mA q Terminal and SBCX not powered. q Measurement performed with impedance analyzer or Siemens K1403. Semiconductor Group 89 Application Guide q Possible problems: - Impedance measurement with 96 kHz exceeds current limit transfer 10 k resistors in S/Tinterface circuitry between transformer and protection circuit (see also S/T-interface recommendation in chapter 4). 3.4.3.6 NT/TE Timing Extraction Jitter q Requirement defined by ITU I.430 sections 8.2.2 and 8.3. q TE timing extraction jitter input data sequences: q q q q - Binary ONEs in 2B+D+E - 40 frames "10" pattern in B1 and B2 and continuous ONEs in D and E channels followed by 40 frames continuous binary ZEROs in 2B+D+E. - Pseudo random pattern with length 2-19 - 1 in 2B+D+E channels The output sequence in all cases consists of binary ZEROs in B1 and B2. Requirement: 14 % of a bit period ( 729 ns) may not be exceeded. = NT jitter requirements input data sequences: - Pseudo random pattern with length 2-19 - 1 in 2B+D channels. The output data sequence consists of binary ONEs in 2B+D channels. Requirement: jitter 5 % of a bit period. The SBCX is in state "F7/G3 Activated" transmitting continuous ZEROs in B1 and B2. For a first jitter evaluation the envelope function of an oscilloscope may be used. Detailed analysis with Siemens K1403. Possible problems: - Technically no problems exist, confusion may be caused by interpretation of results in TE jitter measurements. The specification requires 7 %, due to lack of a fixed reference point this results in 14 % peak to peak tolerance. TE Total Phase Deviation 3.4.3.7 q Requirement defined by ITU I.430 in section 8.2.3. q TE phase deviation input patterns: - Continuous binary ONEs in 2B+D+E - Continuous binary "10" pattern in B1 and B2 combined with continuous binary ONEs in D+E channels. - Continuous binary ZEROs in 2B+D+E - Pseudo random pattern with length 2-19 - 1 in 2B+D+E. Requirement: in addition to the 2 bit default offset the output phase must be within - 7% - + 15 % of a bit period. q The SBCX is in the state "F3 Activated" transmitting continuous ZEROs in B1 and B2. q For a first evaluation an oscilloscope may be used. Detailed analysis with Siemens K1403. q Possible problems: Not known. Semiconductor Group 90 Application Guide 3.4.3.8 TE and NT Longitudinal Conversion Loss (LCL) q Requirement defined by ITU I.430 in section 8.5.6.1. q Measurement conditions: - all possible power feeding conditions. - all possible connections set to ground. - 100 termination across transmit and receive ports. Requirements: template q For LCL tests the SBCX is put into power-off, deactivated and activated condition. The test setup is described in ITU. q Spectrum analyzer and signal generator in combination with S-interface measurement bridge or Siemens K1403. q Possible problems: Not known. 3.4.3.9 TE and NT Output Signal Balance (OSB) q Requirements defined by ITU I.430 in section 8.5.6.2. q Measurement conditions: - all possible power feeding conditions. - all possible connections of the equipment to ground. - 100 termination across transmit and receive ports. Requirements: template. q SBCX is in active state and transmits continuous ZEROs in B1 and B2 channels. For test setup refer to ITU. q Spectrum analyzer and signal generator in combination with S-interface measurement bridge or Siemens K1403. q Possible problems: Not known. 3.4.3.10 q q q q TE Frame Rate Info1 Requirements defined by ITU I.430 in section 8.1 The nominal frame rate of Info1 should be 24 kHz 100 ppm Frequency counter or Siemens K1403 Possible problems: frame rate exceeds limit - adjust oscillator frequency, take crystal with less tolerance Loss and Regain of Frame Alignment (TE) 3.4.3.11 q Values have to be stated in PICS/PIXIT list q SBCX V3.4: m = 3 or 4, n = 2 Semiconductor Group 91 Technical Description 4 Technical Description Chapter 4, "Technical Description", is structured similar to chapter 3 in order to facilitate crossreferencing. Chapter 4 is dedicated to technical information only. It describes the interfaces, control procedures, maintenance functions and the analog line port. The user is intended to refer to chapter 4 when in need of specific technical details. For information on a particular application please refer to chapter 3. 4.1 Interfaces This section describes the interfaces IOM-2, S, and MAI. In addition, a section with technical information on the analog line port (analog receiver and transmitter for the S-interface) was included. All dynamic characteristics are treated in these sections. 4.1.1 General Via the IOM-2 interface data is transmitted in both directions (DU and DD) at half the data clock rate. The data clock (DCL) is a square wave signal with a duty cycle ratio of typically 1:1. Incoming data is sampled on the falling edge of the DCL clock. The frequency is variable and can be set for values ranging from 512 kHz to 4.096 MHz. IOM(R)-2 Interface "a" DCL FSC DU DD Bit 32 Bit 0 Bit 1 Bit 2 ITD04228 Figure 47 IOM(R)-2 Interface Timing The frame clock (FSC) is an 8-kHz signal for synchronizing data transmission on DU and DD. The rising edge of this signal gives the time reference for the first bit transmitted in the first IOM-2 channel. The IOM-2 interface specification describes open drain data lines with external pull-ups. However if operation is logically point-to-point, tristate operation is possible as well. After reset, the SBCX V3.4 senses whether an external pull-up resistor is connected to pin IDP0. If not the SBCX switches automatically to tristate operation (refer to chapter 4.4.3). Semiconductor Group 92 Technical Description Multiframe Marker In NT and LT-S mode the signaling of the multiframe identification on the S-interface is performed automatically by the SBCX. The multiframe generation can be disabled by pin strap (NT pin MAI1 tied to high) or by programming (MFD-bit configuration register). In NT and LT-S mode the S/T-interface superframe with 5 ms period can be synchronized to a master device by modulation of the pulse width of FSC. The SBCX samples the FSC input with the second falling edge of DCL in the very first bit of the frame and resets the S/T-interface transmit frame, including multiframe, if the sample bit is zero. The remaining FSC clocks must be of at least two DCL periods duration. The relationship between the IOM-2 multiframe marker of the slave, the S-interface, and the IOM-2 superframe marker of the master is fixed after activation of the S-interface. I.e. data inserted on LT side in the first B1-channel after the IOM-2 slave superframe marker will always appear on NT side with a fixed offset. The following figure shows the frame relationship between IOM-2 interface and S/T-Interface. FSC S/T Frames No. 19 No. 20 No. 1 No. 2 No. 3 No. 4 ITD04531 Figure 48 S/T-Interface Multi-Frame Synchronization Please note, that in a NT application the superframe marker of IEC-Q must be disabled due to different multiframe periods of U- and S-interface. Power-Down For power saving reasons, the IOM-2 interface can be switched into a "power-down" state (i.e. state "DEACTIVATED" in the status diagram). In this case, the idle state of the data lines are HIGH, while those of the clock lines are LOW. Semiconductor Group 93 Technical Description 4.1.1.1 IOM(R)-2 Dynamic Characteristics In case the period of signals is stated the time reference will be at 1.4 V; in all other cases 0.8 V (LOW) and 2.0 V (HIGH) thresholds are used as reference. The following two diagrams illustrate the timing requirements for TE mode and NT, LT-S or LT-T mode. Timing Characteristics IOM(R)-2 Interface in TE Mode IOM Frame n Channel 2 (...B*-channel) R IOM Frame n + 1 Channel 0 (B1-channel...) R FSC (0) t BCD BCL (0) t WL t DS DCL (0) t FSD t WH tP t DH IDP1 ( ) t DD IDP0 (O) ITD04534 Figure 49 Timing of the IOM(R)-2 Interface in TE Mode Semiconductor Group 94 Technical Description Table 12 Timing Characteristics of the IOM(R)-2 Interface TE Mode Parameter Frame sync delay Bit clock delay Data delay Data setup Data hold Data clock high Data clock low Data clock period Symbol min. Limit Values typ. max. 195 195 100 20 50 175 300 520 325 325 651 475 350 782 ns ns ns ns ns ns ns ns osc 100 ppm osc 100 ppm osc 100 ppm 65 65 Unit Condition tFSD tBCD tDD tDS tDH tWH tWL tP CL = 150 pF CL = 150 pF CL = 150 pF Semiconductor Group 95 Technical Description Timing Characteristics IOM(R)-2 Interface in NT / LT-S and LT-T Mode IOM Frame n lost Channels (...B*-Channel) R IOM Frame n+1 first Channel (B1 Channel...) R t FWH FSC ( ) t FWL t FH DCL ( ) t FS t WH t WL t DS IPD 1 ( ) t DH t DDF t DDC IPD 0 ( O ) ITD04018 Figure 50 Timing of the IOM(R)-2 Interface in NT / LT-S and LT-T Mode Semiconductor Group 96 Technical Description Table 13 Timing Characteristics of the IOM(R)-2 Interface NT / LT-S and LT-T Mode Parameter Data clock high Data clock low Frame sync hold Frame sync setup Frame sync high 1) Frame sync low Data delay to clock Data delay to frame Data setup Data hold Symbol min. Limit Values typ. max. ns ns ns ns ns 100 150 20 50 ns ns ns ns 90 90 30 70 130 Unit Condition tWH tWL tFH tFS tFWH tFWL tDDC tDDF tDS tDH tDCL Note: 1) This is in accordance with the IOM-2 specification. For correct functional operation the high period must be 1 * DCL for multiframe markers and at least 2 DCL periods for non-multiframe markers. Semiconductor Group 97 Technical Description 4.1.1.2 Timing Characteristics CEB (NT / LT-S) The form and the AC characteristics of the CEB input/output (pin X3 in NT and LT-S mode) are given in the following figures for the case of two S/T-interfaces having a minimum loop delay and a maximum loop delay respectively. S/T-Frame TE NT L D L CEB Output t CEBD ITD05204 Figure 51 Timing of the CEB Output S/T-Frame NT TE Bn 7 Bn 8 E CEB Input t CEBS t CEBH ITD05205 Figure 52 Timing of the CEB Input Table 14 Timing Characteristics of the CEB Input / Output Parameter CEB delay CEB setup CEB hold Symbol min. Limit Values typ. max. 5 s s s 3 5 0 Unit Condition tCEBD tCEBS tCEBH CL = 100 pF Semiconductor Group 98 Technical Description The influence of more SBCXs connected to the CEB line is illustrated in the following figure. Two stations one with minimal frame delay (station A), the second with maximum frame delay (station B) determine the echo bit to be sent downstream by evaluating the common echo bit (CEB) line. Figure 53 indicates at what point the CEB value is updated (after reception of D bit on S/T) and when the CEB line is sampled to determine the value of the transmitted echo bit. Station A Binary Values: NT TE Binary Values: TE NT Binary Values: NT TE Binary Values: TE NT Common Echo Bit F L. ED 1 ED 0 ED 1 E D F L. 0 F L. 1 D 0 D 1 D 1 D F L. 1 F L. ED 1 ED 0 ED 1 E D F L. 0 Station B D F L. 1 D 1 D 1 D 0 D F L. 1 1 0 TE are in phase. ITD04535 Condition: All transmit frames NT Figure 53 Functional Timing of the CEB Semiconductor Group 99 Technical Description 4.1.1.3 Structure Command/Indicate Channel 4 bit wide, located at bit positions 27-30 in each time-slot. Verification Double last-look criterion. A new command or indication will be recognized as valid after it has been detected in two successive IOM frames. Codes Both commands and indications depend on the SBCX mode and the data direction. Table 15 presents all defined C/I codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state diagrams in section 4.3 for commands and indications applicable in various states. C/I commands issued by the control device in IOM-1 mode (512 kHz) will be interpreted correctly by the SBCX. Indications sent by the PEB 2081 in 512-kHz modes will also be recognized correctly by a control device operating in IOM-1 mode. Semiconductor Group 100 Technical Description Table 15 C/I Codes Code IN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DR RES TM1 TM2 - - - - AR - ARL - - - - DC LT-S OUT TIM - - - RSY MAIC - - AR - - CVR AI - - DI IN DR RES TM1 TM2 RSY - - - AR - ARL - AI - AIL DC NT OUT TIM - - - RSY MAIC - - AR - - CVR AI - - DI IN TIM RES TM1 TM2 - - - - AR8 AR10 ARL - - - - DI TE/LT-T OUT DR RES TM1 TM2 SLIP 1) RSY MAIC - PU AR - ARL CVR AI8 AI10 AIL DC 1) In LT-T mode only AI AI8 AI10 AIL AR AR8 AR10 ARL CVR DC Activation Indication Activation Indication with high priority Activation Indication with low priority Activation Indication Loop Activation Request Activation Request with high priority Activation Request with low priority Activation Request Loop Code Violation Received Deactivation Confirmation DI DR MAIC PU RES RSY SLIP TIM TIM1 TM2 Deactivation Indication Deactivation Request MAI Change Power-Up Reset Resynchronizing IOM Frame Slip Timer Test Mode 1 (2-kHz signal) Test Mode 2 (96-kHz signal) Semiconductor Group 101 Technical Description 4.1.1.4 Modes Monitor Channel Automode and non-auto mode are available. These affect MON-1 and MON-2 messages only and will be described in the sections dealing with these monitor categories. Structure The structure of the monitor channel is 8 bit wide, located at bit position 17-24 in every time slot. Monitor messages sent to the SBCX are 1 or 2 bytes long, monitor messages returned by the SBCX are 0, 1, 2, or 5 bytes long depending on the command. Transmission of multiple monitor bytes is specified by IOM-2 (see next "Handshake Procedure" for details). For handshake control in multiple byte transfers, bit 31, monitor read "MR", and bit 32 monitor transmit "MX", of every time slot are used. Verification A double last-look criterion is implemented for both bytes of the monitor message. Codes 3 categories of monitor messages are supported by the SBCX V3.4: - MON-1 - MON-2 - MON-8 S1/Q channel S2 channel Register access The order of listing corresponds to the priority attributed to each category. MON-1 messages will be transmitted first, MON-8 messages last in case several messages are initiated simultaneously. Semiconductor Group 102 Technical Description 4.1.1.4.1 Handshake Procedure The monitor channel is full duplex and operates on a pseudo-asynchronous basis, i.e. while data transfer on the bus takes place synchronized to frame synchronization, the flow of monitor data is controlled by the MR and MX bits. Monitor data will be transmitted repeatedly until its reception is acknowledged. Figure 55 illustrates a monitor transfer at maximum speed. The transmission of a 2-byte monitor command followed by a 2-byte SBCX response requires a minimum of 12 IOM-2 frames. In case the controller is able to confirm the receipt of first SBCX response byte in the frame immediately following the MX transition on DOUT from HIGH to LOW (i.e. in frame No. 6), 1 IOM frame may be saved. Note: Transmission and reception of monitor messages can be performed simultaneously by the SBCX. This feature is used by the SBCX to send back the response before the transmission from the controller is completed (SBCX does not wait for EOM from controller). M1/2: R1/2: Monitor message 1. and 2. byte Monitor response 1. and 2. byte IOM R -2 Frame No. 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 Tx 1.Byte ~ ~ Tx 2.Byte EOM Ack. 1.Byte ~ ~ ~ ~ MX IDP 1 MR Mon. Data IDP 1 Ack. 2.Byte ~ ~ ~ ~ EOM FF M1 M1 M2 M2 1 0 Ack. 1.Byte FF FF FF FF FF FF FF Tx 1.Byte MX IDP 0 MR Mon. Data IDP 0 1 0 FF FF FF FF Tx 2.Byte EOM Ack. 2.Byte EOM R1 R1 R1 R2 R2 FF FF FF ITD05302 Figure 54 Handshake Protocol with a 2-Byte Monitor Message/Response Idle State After the bits MR and MX have been held inactive (i.e. HIGH) for two or more successive IOM frames, the channel is considered idle in this direction. Semiconductor Group 103 Technical Description Standard Transmission Procedure 1. The first byte of monitor data is placed by the external controller (e.g. ICC, EPIC) on the IDP1 line of the SBCX and MX is activated (LOW; frame No 1). 2. The SBCX reads the data of the monitor channel and acknowledges by setting the MR bit of IDP0 active if the transmitted bytes are identical in two received frames (frame No. 2 because the PEB 2081 reads and compares data already while the MX bit is not activated). 3. The second byte of monitor data is placed by the controller on IDP1 and the MX bit is set inactive for one single IOM frame. This is performed at a time convenient to the controller. 4. The SBCX reads the new data byte in the monitor channel after the rising edge of MX has been detected. In the frame immediately following the MX transition active-to-inactive, the MR bit of IDP0 is set inactive. The MR transition inactive-to-active exactly one IOM frame later is regarded as acknowledgment by the external controller (frame No. 4-5). The response of the SBCX will always be sent immediately after the 2. byte has been received and acknowledged. 5. After both monitor data bytes have been transferred to the SBCX, the controller transmits "End of Message" (EOM) by setting the MX bit inactive for two or more IOM frames (frame No. 5-6). 6. In the frame following the transition of the MX bit from active to inactive, the SBCX sets the MR bit inactive (as was the case in step 4). As it detects EOM, it keeps the MR bit inactive (frame No. 6). The transmission of the monitor command by the controller is complete. 7. If the SBCX is requested to return an answer it will commence with the response as soon as the second controller byte was acknowledged (i.e. response starts in frame 5). The procedure for the response is similar to that described in points 1-6 except for the transmission direction. It is assumed that the controller does not latch monitor data. For this reason one additional frame will be required for acknowledgment. Transmission of the 2. monitor byte will be started by the SBCX in the frame immediately following the acknowledgment of the first byte. The PEB 2081 does not delay the monitor transfer. Semiconductor Group 104 Technical Description Error Treatment and Transmission Abortion In case the SBCX does not detect identical monitor messages in two successive frames, transmission is not aborted. Instead the SBCX will wait until two identical bytes are received in succession. Transmission is aborted only if errors in the MR/MX handshake protocol occur. An abort is indicated by setting the MR bit inactive for two or more IOM-2 frames. The controller must react with EOM. This situation is illustrated in the following figure. IOM -2 Frame MX IDP 1 MR MX IDP 0 MR R No. 1 0 1 0 1 0 1 0 1 2 3 4 5 EOM 6 7 Abort Request from Receiver ITD05306 Figure 55 Abortion of Monitor Channel Transmission 4.1.1.4.2 Monitor Procedure Timeout (TOD) The PEB 2081 V3.4 can operate with or without the "Monitor Timeout Procedure". The TOD bit in the SM/CI (Timeout Disable) controls the timeout function. TOD = ZERO enables the function, TOD = ONE disables it. With the timeout procedure enabled, the SBCX checks the monitor status once per multi-frame. This check is performed at the same time the 20th (i.e. last) S-frame is transmitted within the S-interface multi-frame structure. In case the monitor is active the current status of the monitor channel is saved. This condition will be compared with the status at the next check (i.e. 5 ms later). If the condition of the monitor channel has not changed within this period the SBCX assumes a lock-up situation. The SBCX will resolve this lock-up situation by transmitting on IDP0 a EOM (End of Message) command (MX bit set to ONE for 2 IOM frames). After the transmission of EOM the SBCX will retransmit the previous monitor channel data. No monitor channel data will therefore be lost. Semiconductor Group 105 Technical Description 4.1.1.4.3 MON-1, MON-2 Commands (S/Q Channel Access) Function: MON-1 and MON-2 commands provide access to the SBCX internal S/Q registers. MON1 controls the S1 and Q channel, MON-2 controls the S2 channel on the S-interface. In order to synchronize onto multiframing pulses (TE, LT-T modes) and issue monitormessages (NT, LT-S modes) the MFD (Multi-frame disable) bit in the configuration register must be set to ZERO. MON-1 and MON-2 commands may be passed at any instant provided the S-interface is activated. They are always one byte long. Direction S IOM: In the direction S-interface to IOM interface a 1 byte buffer is implemented. Every time a S/Q message has been received on the S-interface which needs to be forwarded to the IOM interface this message will be saved in a latch. This latch allows retransmission of the old S/Q data on IOM in case the message has not been read by the controller before a monitor timeout occurred. While the latched data has not been read correctly from the monitor channel the S/Q receiver will not reload the latch. Thus the IOM controller must read out the S/Q messages from IOM once per 5 ms (multi-frame period). If this is not guaranteed S/Q channel data may be lost. Direction IOM S: No buffering is available in the direction IOM-interface to S-interface. The SBCX will acknowledge a S/Q command correctly and transfer the command into an internal S/Q transmit buffer if this command is received during frame numbers 1-17. Once a command has been transferred into the internal transmit register new S/Q commands received during frames 1-17 will not be accepted by the SBCX (i.e. no acknowledgment issued with MR bit). During frame numbers 18-20 however the monitor channel data is transferred directly into the transmit register. During this period previously accepted S/Q data could therefore be overwritten. To avoid this situation the controller must be programmed to send no more than one S/Q command per multiframe (5 ms). Note that for both S1 and S2 channel a separate transmit register is reserved. The above stated restriction thus applies only to S/Q commands referring to the same channel. Transmission of the stored data will commence with the new multi-frame. Priority: Modes: MON-1 commands have the highest priority, MON-2 command are treated with second priority. Non-auto mode and transparent mode are available in all operational modes. The SQM (SQ Mode) bit selects transparent mode (ONE) and non-auto mode (ZERO). Semiconductor Group 106 Technical Description Non-Auto Mode In non-auto mode only MON-1 functions to access the S1 and Q channel are available. MON-2 messages (for S2 channel access) are ignored. In non-auto mode monitor messages are only released after new data has been received. In this mode traffic on the IOM monitor channel is reduced. The controller only receives changes in the S1 or Q channel reducing its processing demands as well. Transparent Mode In transparent mode all S/Q channels are available to the user. MON-1 commands/messages service the S1 and Q channel, MON-2 commands/messages related exclusively to the S2 channel. In this mode the data received on S1, S2 or Q will be forwarded directly to the IOM-interface. No comparison with previously sent data is performed so that one MON-1 and one MON-2 monitor message will be issued every 5 ms (once per multi-frame) in TE or LT-T modes. In NT and LT-S modes one MON-1 message will indicate every multi-frame the current Q channel data received. Codes: MON-1 Command/Message (S1/Q channel) 1 Byte 0 0 0 MON-1 S1: Q: 1 S1/Q S1/Q S1/Q Data S1/Q Data in S1 channel (NT, LT-S input; TE, LT-T output) Data in Q channel (TE, LT-T input; NT, LT-S output) MON-2 Command/Message (S2 channel) 1 Byte 0 0 1 MON-2 S2: 0 S2 S2 S2 Data S2 Data in S2 channel (NT, LT-S input; TE, LT-T output) Currently neither S1, S2 nor Q channel commands have been standardized. Semiconductor Group 107 Technical Description 4.1.1.4.4 MON-8 Commands (Register Access) Function: MON-8 commands provide access to the SBCX internal registers. MON-8 commands allow to configure the SBCX. With the exception of the identification register (read only) all registers have read/write capability. In case a write operation is selected the command is two bytes long. For a read operation the two byte long read request command will be followed by a two byte long response message. Only exception is a read request from the P MAI interface. Here a single 5 byte response monitor message is optional. Buffering: After hard- or software reset, the register values specified in "Initial State" overwrite all customer settings. Modifications in the internal registers will be latched until they are overwritten with a new MON-8 command. Modes: MON-8 commands are independent of the operational SBCX mode or other mode selections. Depending on the operational mode the meaning of single register bits may change. Codes Write to Register Structure 1. Byte 1 0 0 0 r r r r D7 D6 D5 MON-8 r: D0-D7: Register Address Write Data Reg. Address 2. Byte D4 D3 D2 D1 D0 Register Data Write - 1 ... 5 (Configuration Reg. - MAI Pin Reg.) - Depending on Register Read Register Request Structure 1. Byte 1 0 0 0 0 0 - 0 0 0 0 - 0 MON-8 r: Register Address 2. Byte 0 r r r r Reg. Address - 0 ... 5 (Identification Reg. - MAI Pin Reg.) Read Response Structure 1. Byte 1 0 0 0 r r r r D7 D6 D5 MON-8 r: D7 ... D0: Reg. Adr. 2. Byte D4 D3 D2 D1 D0 Register Data Read Register Address Confirmation - 0 ... 5 (Identification Reg. - MAI Pin Reg.) Receive Data - Depending on Register Semiconductor Group 108 Technical Description MON-8 Identification Register - (Read, Address: 0H) Format: Initial Value: 42H Older SBCX Versions identify themself with the following IDs: Versions: Versions: A1 to A3 B1 and 2.2 ID = 40H ID = 41H 0 1 0 0 0 0 1 0 MON-8 Configuration Register - (Read/Write, Address: 1H) Format: Initial Value: 00H Table 16 Bit-name MODE C/W/P Description Pin MODE = VDD (LT-S, LT-T): 0: LT-S mode selected 1: LT-T mode selected MFD MAIM FSMM LP SQM RCVE C/W/P MODE LT-S and NT mode: Configuration 0: point-to-point or extended passive bus configuration (adaptive timing recovery). In NT mode the pin X0 (= BUS) must be low. 1: short passive bus configuration (fixed timing recovery) in LT-T mode: Wander detection (warning in C/I, data may be lost!) 0: "SLIP" after 50 s wander 1: "SLIP" after 25 s wander in TE mode: Power converter clock frequency supplied at pin 40 0: 32 kHz 1: 16 kHz SQM SQ channel handling mode selection 0: non automode only S1 and Q channels 1: transparent mode S1, S2 and Q channels 0: 1: normal operation Far-end-code-violation (FECV) function according to ANSI T1.605 implemented. After each multiframe the receipt of at least one illegal code violation is indicated by the occurance of six times the C/I code 1011(CVR). RCVE LP NT/LT-S mode: 0: transparent analog loop 1: non-transparent analog loop TE / LT-T mode: 0: non-transparent analog loop 1: external transparent loop Semiconductor Group 109 Technical Description Table 16 (cont'd) FSMM NT/LT-S mode: 0: normal operation 1: Finite state machine interchanged (LT-S N) MAI pins mode: 0: I/O-specific or standard I/O MAI interface 1: P interface mode for MAI interface Multi-frame disable (write): 0: All multi-frame functions active. In NT mode the pin MAI1 (= MFD) must be low. 1: Multi-frame generation (NT, LT-S) or synchronization (TE, LT-T) prohibited. No SQ monitor messages released. Multi-frame detected (read): 0: No multi-frame synchronization achieved. 1: Multi-frame synchronization achieved. MAIM MFD MON-8 Loop-Back Register - (Read/Write, Address: 2H) Format: Initial value: 02H Table 17 Bit-name AST Description ASynchronous Timing NT and LT-S mode; only NT state machine 0: LT-S: command TIM in C/I NT: asynchronous wake up 1: LT-S: asynchronous wake up (useful for the Intelligent NT) NT: command TIM in C/I Loop-back B1 channel at S/T-interface in LT-S/NT-mode Loop-back B2 channel at S/T-interface in LT-S/NT-mode Loop-back complete (2B+D) at S/T-interface in LT-S/NT-mode Loop-back B1 channel at IOM-2 interface Loop-back B2 channel at IOM-2 interface Loop-back B1 into B2 channel and vice versa at IOM-2 interface. Additionally IB1 and/or IB2 must be set. AST SB1 SB2 SC IB1 IB2 1 IB12 SB1 SB2 SC IB1 IB2 IB12 Semiconductor Group 110 Technical Description MON-8 IOM-2 Channel Register - (Read/Write, Address: 3H) Format: Initial value: 00H Table 18 Bit-name B1L Description B1 channel location 0: normal 1) 1: B1 channel in IOM-2 channel 0 B2 channel location 0: normal 1) 1: B2 channel in IOM-2 channel 0 D-channel location 0: normal 1) 1: D-channel in IOM-2 channel 0 CI channel location 0: normal 1) 1: in IOM-2 channel 0 B1 channel direction 0: normal (IDP0 is data output, IDP1 is data input) 1: IDP0 and IDP1 interchanged for B1 channel B2 channel direction 0: normal (IDP0 is data output, IDP1 is data input) 1: IDP0 and IDP1 interchanged for B2 channel D-channel handling 0: LT-S, LT-T and NT mode: transparent TE mode: collision detection according to ITU I.430 (BAC and A/B bit evaluation) 1: NT and LT-S mode: D-channel access control TE mode: transparent D-channel LT-T mode: D-channel collision resolution according to ITU I.430 CI channel handling 0: normal C/I access in the pin strapped IOM-2 channel 1: disabled, access to C/I is only possible via the SM/CI register B1L B1D B2L B2D DL DH CIL CIH B2L DL CIL B1D B2D DH CIH Notes: 1) In LT-S and LT-T mode: pin strapped IOM-2 channel In NT and TE mode: IOM-2 channel 0 Semiconductor Group 111 Technical Description MON-8 SM/CI Register - (Read/Write, Address: 4H) Format: Initial value: CI, 0H Table 19 Bit-name CI (3:0) Description CI channel When CIH-bit is set to one the commands are input in the monitor channel CI (3:0) The indication can always be read via monitor channel CI (3:0) Time-Out Disable 0: monitor timeout (minimum 5 ms) enabled 1: monitor timeout disabled Stop / Go Enable 0: normal 1: In TE mode pin MAI5 outputs S/G signal Maintenance Input Output (MAIM = 0) 0: I/O-specific functions on MAI interface 1: Standard I/O function on MAI interface CI3 CI2 CI1 CI0 TOD SGE 0 MIO TOD SGE MIO Semiconductor Group 112 Technical Description MON-8 MAI Pin Register - (Read/Write, Address: 5H) Format: Initial value: 00H MPR7 MPR6 MPR5 MPR4 MPR3 MPR2 MPR1 MPR0 Bit-name Description MPR (7:0) access to MAI(7:0) pins if MAI interface is set to standard I/O or I/O specific function mode. In case the P interface was selected for the MAI interface mode (MAIM = 1) the MAI pin register are defined as follows (only "write to register" operation will be accepted). Format: (write only) WR RD A1 A0 INT D2 D1 D0 Table 20 Bit-name D0...D2 MAI0:2 INT (MAI3) A0 ... A1 (MAI4:5) RD (MAI6) WR (MAI7) Description Data pin (input/output) Interrupt (input), Read request control: 0: Single Address read operation 1: Complete address (0...3) read operation. Address pins (output) Read signal (output) 0: Read operation 1: Write operation (if WR = 0) Write Signal (output). 0: Write operation 1: Read operation (if RD = 0) Semiconductor Group 113 Technical Description 4.1.2 S/T-Interface Transmission over the S/T-interface is performed at a rate of 192 kbit/s. Pseudo-ternary coding with 100 % pulse width is used (see following section). 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance information. The SBCX uses two symmetrical, differential outputs (SX1, SX2) and two symmetrical, differential inputs (SR1, SR2). These signals are coupled via external circuitry and two transformers onto the 4 wire S-interface. The nominal pulse amplitude on the S-interface is 750 mV (zero-peak). 4.1.2.1 S/T-Interface Coding The following figure illustrates the code used. A binary ONE is represented by no line signal. Binary ZEROs are coded with alternating positive and negative pulses with a single exception: the first binary ZERO following the framing balance bit is of the same polarity as the framing-balancing bit (required code violation). Semiconductor Group 114 Technical Description 0 +V 0V -V 1 0 0 1 1 0 0 0 1 1 ITD00322 Figure 56 S/T -Interface Line Code (without code violation) A standard S/T frame consists of 48 bits. In the direction TE NT the frame is transmitted with a two bit offset. For details on the framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the standard frame structure for both directions (NT TE and TE NT) with all framing and maintenance bits. 48 Bits in 250 s D L. F L. NT 0 TE 1 0 2 Bits Offset B1 E D A FA N B2 E DM B1 EDS B2 E D L. F L. D L. F L. TE NT 0 1 0 B1 L. D L. FAL. B2 L. D L. B1 L. D L. B2 L. D L. F L. t ITD03993 Figure 57 Frame Structure at Reference Points S and T (ITU I.430) Semiconductor Group 115 Technical Description -F - L. -D -E - FA -N - B1 - B2 -A -S -M Framing Bit D.C. Balancing Bit D-Channel Data Bit D-Channel Echo Bit Auxiliary Framing Bit B1-Channel Data Bit B2-Channel Data Bit Activation Bit S-Channel Data Bit Multiframing Bit F = (0b) identifies new frame (always positive pulse) L. = (0b) number of binary ZEROs sent after the last L. bit was odd Signaling data specified by user E = D no D-channel collision. ZEROs overwrite ONEs See section 6.3 in ITU I.430 N = FA User data User data A = (0b) INFO 2 transmitted A = (1b) INFO 4 transmitted S1 or S2 channel data M = (1b) Start of new multi-frame Semiconductor Group 116 Technical Description 4.1.3 S/T-Interface Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer 1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Q-channel). The Q bits are defined to be the bits in the FA bit position. In the NT-to-TE direction the S channel bits are used for information transmission. Two S channels (S1 and S2) out of five possible S channels can be accessed by the SBCX. The S and Q channels are accessed via the IOM-2 interfaces monitor channel. The following table shows the S and Q bit positions within the multi-frame. Table 21 Frame Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 NT-to-TE FA Bit Position ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO NT-to-TE M Bit ONE ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ONE ZERO NT-to-TE S Bit S11 S21 ZERO ZERO ZERO S12 S22 ZERO ZERO ZERO S13 S23 ZERO ZERO ZERO S14 S24 ZERO ZERO ZERO S11 S21 TE-to-NT FA Bit Position Q1 ZERO ZERO ZERO ZERO Q2 ZERO ZERO ZERO ZERO Q3 ZERO ZERO ZERO ZERO Q4 ZERO ZERO ZERO ZERO Q1 ZERO Semiconductor Group 117 Technical Description In TE and LT-T mode the SBCX identifies the Q-bit position (after multi-frame synchronization has been established) by waiting for the FA bit inversion in the received S/T-interface data stream (FA [NT TE] = binary ONE). After successful identification, the Q data will be inserted at the upstream (TE NT) FA bit position. When synchronization is not achieved or lost, it mirrors the received FA bits. Multi-frame synchronization is achieved after two complete multi-frames have been detected with reference to FA/N bit and M bit positions. Multi-frame synchronization is lost after two or more bit errors in FA/N bit and M bit positions have been detected in consequence, i.e. without a complete valid multi-frame between. The multi-frame synchronization can be disabled by programming (MFD-bit configuration register). 4.1.4 Maintenance Auxiliary Interface (MAI) Selection of MAI interface configuration: Table 22 Configuration Reg. MAIM 0 0 1 1 SM/CI Reg MIO 0 1 0 1 MAI Interface Mode I/O specific Standard I/O P interface mode not applicable After a hard- or software reset the default setting is "I/O specific" interface. 4.1.4.1 I/O Specific Mode Please refer to section 3.2.3.1 in the application chapter for details on the I/O specific signals. Register access is performed as described for standard I/O mode. Semiconductor Group 118 Technical Description 4.1.4.2 Standard I/O Mode Provides four input and four output lines. Interface access via MON-8 MAI pin register. The MAI pins may be written by the following 2-byte sequence via the IOM-2 monitor channel: Write message (to SBCX) write command (access to MAI Pin Register MPR) 85H *** means don't care data D(7:4) to be written to MAI pin (7:4) D7 D6 D5 D4 **** The MAI pins may be read by the following 2-byte sequence via the IOM-2 monitor channel: Read message (to SBCX) read command 80H response (from SBCX) 8 + internal address (i.e. MPR) 85H data D7 D6 D5 D4 D3 D2 D1 D0 MAI pin Register MPR 05H where D(7:4) are the previously written MAI (7:4) bits and D(3:0) are the MAI (3:0) inputs. Semiconductor Group 119 Technical Description 4.1.4.3 P MAI Mode In case the P mode is selected (MIO, MAIM bits) the following timing applies for read and write operations. Write Access RD t wRL WR t sAD A 0 ... A 1 t dDWS D 0 ... D 2 t dDWE ITD05202 Figure 58 Dynamic Characteristics of P Interface Write Access Read Access RD t rDL WR t sAD A 0 ... A 1 t sDR D 0 ... D 2 t hDR ITD05203 Figure 59 Dynamic Characteristics of P Interface Read Access Semiconductor Group 120 Technical Description Table 23 Dynamic Characteristics of Data Port Parameter Write Width Low Address Delay Read/Write Data Delay Write Start Data Delay Write End Setup Data Read Hold Data Read Read Width Low Interrupt For every change at the input pin "INT", the SBCX V 3.4 will transmit a C/I channel code (0101b), MAIC, in 4 successive IOM-2 frames. The INT pin is sampled continuously. Monitor Message Sequences MAI "write" message (from SBCX to e.g. IEPC) 1 0 0 0 0 1 0 1 0 1 address * data Signal Abbreviation Min. Typ. Max. Units ns 2 x DCL + 200 ns + 200 ns ns ns ns twRL A0 ... 1 tsAD D0 ... 2 tdDWS 2 x DCL - 200 2 x DCL - 200 - 200 1 x DCL - 200 100 50 2 x DCL - 200 tdDWE tsDR thDR trDL 1 x DCL + 200 ns MAI "single read" message (from SBCX to e.g. IEPC) 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 address address 1 1 * * data * MAI "single read" response (response from e.g. IEPC to SBCX) MAI "multiple read" message MAI (from SBCX to e.g. IEPC) 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 *** means don't care data Data(2:0) address Address(1:0) 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 * * data data data data * MAI "single read" response (response from e.g. IEPC to SBCX) Semiconductor Group 121 Technical Description 4.2 Control Procedures Chapter 4.2 illustrates the interactions between two SBCX stations during activation and deactivation. The behaviour of a single SBCX station is described in the state diagrams of chapter 4.3. With a knowledge of the state machine and the interactions involved, it is possible to predict the behaviour of the device under all conditions. The activation and deactivation procedures implemented by the SBCX in its different operating modes were designed according to ITU I.430. The following table explains all S/T-interface signals used in the following sections (definition in ITU I.430). Table 24 S/T-Interface Signals Signals from NT to TE INFO 0 No signal. Signals from TE to NT INFO 0 INFO 1 No signal. A continuous signal with the following pattern: Positive ZERO, negative ZERO, six ONEs. INFO 2 Frame with all bits of B, D, and D-echo channels set to binary ZERO. Bit A set to binary ZERO. N and L bits set according to the normal coding rules. INFO 3 Synchronized frames with operational data on B and D-channels. INFO 4 Frames with operational data on B, D, and D-echo channels. Bit A set to binary ONE. Semiconductor Group 122 Technical Description 4.2.1 Complete Activation Initiated by Exchange (LT-S) The following figure depicts the procedure if activation has been initiated by the exchange side and the exchange SBCX is set to LT-S mode. IOM -2 DC DI R TE/LT-T S/T Interface INFO 0 INFO 0 LT-S IOM -2 DC DI AR AR R RSY AR AI AR8 / AR10 INFO 2 INFO 0 INFO 3 INFO 4 AI SBCX SBCX ITD05122 Figure 60 Complete Activation Initiated by Exchange (LT-S) Semiconductor Group 123 Technical Description 4.2.2 Complete Activation Initiated by Exchange (NT) Figure 61 illustrates the activation procedure when the exchange starts the activation. IOM -2 DC DI R TE/LT-T S/T Interface INFO 0 INFO 0 NT IOM -2 DC DI AR AR R RSY AR INFO 2 INFO 0 INFO 3 INFO 4 AI AI AI AR8 / 10 SBCX SBCX U-Interface Device ITD05123 Figure 61 Complete Activation Initiated by Exchange (NT) Semiconductor Group 124 Technical Description 4.2.3 Complete Activation Initiated by Terminal The following figure illustrates the activation process if started from the terminal side (or LT-T). This illustration only shows the part of the activation which differs from the previously described exchange initiated activation. IOM -2 DC DI R TE/LT-T S/T Interface INFO 0 INFO 0 LT-S/NT IOM -2 DC DI R TIM PU AR8 / AR10 INFO 0 INFO 1 INFO 0 INFO 2 AR RSY SBCX SBCX U-Interface Device ITD05124 Figure 62 Complete Activation Initiated by TE In the case where activation is requested from a terminal, the NT SBCX first requests timing on the IOM-2 interface by pulling DU (Data upstream line) to a static low level. The length of the low level is programmable (AST-bit of the Loop-Back Register). The SBCX enters the power-up state immediately after timing has been applied. Semiconductor Group 125 Technical Description 4.2.4 Complete Deactivation A deactivation will always be initiated by the exchange side. IOM -2 AI DI (AR) R TE/LT-T S/T Interface INFO 4 INFO 3 LT-S/NT IOM -2 AR (AI) AI DR TIM R DR DI DC INFO 0 INFO 0 32 ms DI DC SBCX SBCX ITD05125 Figure 63 Deactivation Procedure For the NT case (DCL = 512 kHz) the deactivation procedure is shown in the following figure. After detecting the code DI (Deactivation Indication) from the downstream unit SBCX, the upstream unit responds by transmitting DC (Deactivate Confirmation) during subsequent frames and stops the timing signals synchronously with the end of the last C/I channel bit of the fourth frame. Please note, in the deactivated state the oscillator is switched off. Semiconductor Group 126 Technical Description a) FSC DI DU DR DD DR DC DC DC DC DI DI DI DI DI IOM -2 Interface deactivated R Detail see Fig.b b) DCL IOM -2 Interface deactivated R DU D C/ C/ C/ C/ ITD04530 Figure 64 Deactivation of the IOM(R)-2 Interface in the NT (DCL = 512 kHz) Semiconductor Group 127 Technical Description 4.3 State Machine State machines are the key to understanding the SBCX in different operational modes. They include all information relevant to the user and enable him to understand and predict the behaviour of the SBCX. The informations contained in the state diagrams are: - - - - - state name (based on ITU I.430) S/T signal transmitted C/I code received C/I code transmitted transition criteria It is essential to be able to interpret the state diagrams. SBCX OUT SBCX IN C/ S / T Interface INFO Ind. Cmd. Unconditional Transition State ix ir ITD04009 Figure 65 State Diagram Notation The following example illustrates the use of a state diagram with an extract of the TE state diagram. The state explained is "F3 power down". The state may be entered by either of two methods: - from state "test mode i" after the C/I command "DI" has been received. - from state "F3 pending deactivation" after the C/I command "DI" been received. The following informations are transmitted: - INFO 0 (no signal, see chapter 4.2) is sent on the S/T-interface. - C/I message "DC" is issued on the IOM-2 interface. Semiconductor Group 128 Technical Description The state may be left by either of the following methods: - Leave for the state "F3 power up" after synchronous or asynchronous "TIM" code has been received on IOM. - Leave for state "F5/8 unsynchron" after any kind of signal (not INFO 0) has been recognized on the S/T-interface. - Leave for state "F4 pending activation" in case C/I = AR8 or AR10 is received and the MAI pin CON is set to high (i.e. INFO 1 transmission not disabled). As can be seen from the last transition criteria described combinations of multiple conditions are possible as well. A "&" stands for a logical AND combination. An "or" indicates a logical OR combination. The sections following the state diagram contain detailed information on all states and signals used. These details are mode dependent and may differ for identically named signals/states. They are therefore listed for each mode. 4.3.1 State Machine TE/LT-T Modes Section 4.3.1 is applicable for both TE and LT-T operational modes. Semiconductor Group 129 Technical Description 4.3.1.1 TE/LT-T Modes State Diagram DC DI TIM DI TIM TMI TMI 5) Test Mode i it * F3 Power Down i0 ARp & CON i0 DI TIM ARp & CON DI i0 PU AR p 3) F4 Pend. Act. i1 i0 2) PU TIM DIS F3 Power Up i0 i0 i0 TMI Any State i0 RSY i4 X F5/8 Unsynchron i0 i1 i2 i0 X DI 2) 1) Reset/Loop TIM AR X 2) i2 & i4 RST Any State RES + ARL F6 Synchronized i3 i4 AI p 4) i2 i2 X 2) DI i2 & i4 i0 DR AR TIM F7 Activated i3 Slip SLIP i2 X 2) F3 Pend. Deact. i0 i0 i4 0.5 ms i2 & i4 TIM IN IOM R Ind. Cmd. F7 Slip Detected i3 i4 S/T ix State ir ITD04010 Notes: 1. See state diagram for unconditional transitions for details 2. x = TM1 or TM 2 or RES or ARL x = TM1 & TM2 & RES & ARL 3. ARP = AR8 or AR10 4. AIP = AI8 or AI10 5. TMI = TM1 or TM2 Figure 66 State Transition Diagram in TE/LT-T Modes Semiconductor Group 130 Technical Description Any F3 State Power Up ARL DI ARL TIM RES i3 i3 * i3 1) Pin-RES ARL ARL RES RES DI * Loop A Closed TIM i0 Reset RSY ARL AIL Loop A Activated DI i3 * RES TIM RES IOM Any State S/T ix R OUT IN Ind. Cmd. State ir ITD04011 Note: 1. In state "loop A activated" I3 is the internal signal, the external signal is I0. Figure 67 State Diagram of the TE/LT-T Modes, Unconditional Transitions Semiconductor Group 131 Technical Description 4.3.1.2 TE/LT-T Modes Transition Criteria The transition criteria used by the SBCX are described in the following sections. They are grouped into: - C/I commands - Pin states - Events related to the S/T-interface 4.3.1.2.1 C/I Commands AR8 Activation Request with priority 8 for D-channel transmission. This command is used to start a TE initiated activation. D-channel priority 8 is the highest priority. It should be used to request signaling information transfer. Activation request with priority 10 for D-channel transmission. This command is used to start a TE initiated activation. D-channel priority 10 is the lower priority. It should be used to request packet data transfer. Activation request loop. The SBCX is requested to operate an analog loop-back close to the S/T-interface. ARL is an unconditional command. Deactivation indication. This command transfers the SBCX into "F3 power down" mode and disables the IOM-2 clocks. Reset of state machine. Transmission of Info 0. No reaction to incoming infos. RES is an unconditional command. All MAI pins are tristate during RST = 0 or when the SBCX is in the state "reset", unless MAIM is programmed to 1. After reset four pins, MAI (3:0), are operated as input pins and four pins, MAI (7:4), as output pins (push/pull). The value after reset is 0. TIM TM1 Timing Request. Requests the SBCX to change into power-up state and provide timing signals on IOM-2. Test Mode 1. Transmission of single pulses on the S/T-interface. The pulses are transmitted with alternating polarity at a frequency of 2 kHz. TM1 is an unconditional command. Test Mode 2. Transmission of continuous pulses on the S/T-interface. The pulses are sent with alternating polarity at a rate of 96 kHz. TM2 is an unconditional command. AR10 ARL DI RES TM2 Semiconductor Group 132 Technical Description 4.3.1.2.2 Pin States Pin-RES Pin-Reset. Corresponds to a low level at pin RST. At power up, a reset pulse (RST low active) of minimum 1 s should be applied to bring the SBCX to the state "reset". After that the SBCX may be operated according to the state diagrams. In NT mode the DCL is needed during the hardware reset (RES = 0) for initialization. The devices working together with the SBCX in NT mode (i.e. IECs and IBC) automatically deliver the necessary clocks. The function of this pin is identical to the C/I code RES concerning the state machine. A low at this input disables the TE/LT-T activation capability by preventing INFO 1 to be sent. This pin is used in conjunction with power-controllers to control activation capability under emergency power conditions. Pin-CON 4.3.1.2.3 S/T-Interface Events I0 I0 I2 I4 SLIP INFO 0 detected A signal different to INFO 0 was detected INFO 2 detected INFO 4 detected SLIP detected (applicable in LT-T mode only) IOM-2 interface framing and S/T-interface framing differences have exceeded the specified limit. It is likely that data will be lost to enable a resynchronization. Transmitted Signals and Indications in TE/LT-T Modes 4.3.1.3 The following signals and indications are issued on the IOM-2 and S/T-interface. Semiconductor Group 133 Technical Description 4.3.1.3.1 C/I Indications Abbreviation DR RES TM1 TM2 SLIP Indication Deactivate Request Reset Test mode 1 Test mode 2 Slip detected (LT-T only) Resynchronization during level detect MAI change Disconnected Power up Activate request Activate request loop Far-end-code-violation Remark Deactivation request via S/T-interface Reset acknowledge TM1 acknowledge TM2 acknowledge Wander is larger than 50 s peak-to-peak (or 25 s peak-to-peak if programmed, refer to the C/W/P-bit of the Configuration Register) Signal received, receiver not synchronous Pin MAIn has changed Pin CON (pin MAI1) connected to GND IOM-2 interface clocking is provided Info 2 received Loop A closed After each multi-frame the receipt of at least one illegal code violation is indicated six times. This function must be enabled by setting the RCVE-bit in the configuration register. Loop A activated Info 4 received, D-channel priority is 8 or 9 Info 4 received, D-channel priority is 10 or 11 Clocks will be disabled, (in TE), quiescent state RSY MAIC DIS PU AR ARL CVR AIL AI8 AI10 DC Activate indication loop Activate indication with priority class 8 Activate indication with priority class 10 Deactivate confirmation 4.3.1.3.2 S/T-Interface Signals I0 I1 I3 It INFO 0 INFO 1 INFO 3 Pseudo-ternary pulses at 2 kHz frequency (alternating, TM1) Pseudo-ternary pulses at 96 kHz frequency (alternating, TM2) Semiconductor Group 134 Technical Description 4.3.1.4 States TE/LT-T Mode F3 power down This is the deactivated state of the physical protocol. The received line awake unit is active. In TE mode, clocks are disabled. F3 power up This state is dependent of the logical level of CON (pin MAI1) CON = 1: This state is similar to "F3 power down". The state is invoked by a C/I command TIM = "0000" (or DI static low). After the subsequent activation of the clocks the "Power Up" message is output. CON = 0: This state is similar to "F3 power down". The state is invoked by a C/I command TIM = "0000" (or DI static low). After the subsequent activation of the clocks the "Disconnected" message is output. F3 pending deactivation The SBCX reaches this state after receiving INFO0 (from states F5 to F8) from F6 and F7 via F5/8. From this state an activation is only possible from the line (transition "F3 pend. deact." to "F5 unsynchronized"). The power down state may be reached only after receiving DI. F4 pending activation Activation has been requested from the terminal, INFO 1 is transmitted, INFO 0 is still received, "Power Up" is transmitted in the C/I channel. This state is stable: timer T3 (I.430) is to be implemented in software. F5/8 unsynchronized At the reception of any signal from the NT, the SBCX ceases to transmit INFO 1, adapts its receiver circuit, and awaits identification of INFO 2 or INFO 4. This state is also reached after the SBCX has lost synchronism in the states F6 or F7 respectively. F6 synchronized When the SBCX receives an activation signal (INFO 2), it responds with INFO 3 and waits for normal frames (INFO 4). F7 activated This is the normal active state with the layer 1 protocol activated in both directions. From state "F6 synchronized", state F7 is reached almost 0.5 ms after reception of INFO 4. Semiconductor Group 135 Technical Description F7 slip detected When a slip is detected between the S/T-interface clocking system and the IOM-2 interface clocks (phase wander greater than 50 s, data may be disturbed, or 25 s if programmed in the configuration register) the SBCX enters this state, synchronizing again the internal buffer. After 0.5 ms this state is left again (only possible in LT-T mode). Unconditional States TE/LT-T Mode Loop A closed On Activate Request Loop command, INFO 3 is sent by the line transmitter internally to the line receiver (INFO0 is transmitted to the line). The receiver is not yet synchronized. Loop A activated The receiver is synchronized on INFO 3 which is looped back internally from the transmitter. Data may be sent. The indication "AIL" is output to indicate the activated state. When the S/T line awake detector, which is switched to the line, detects an incoming signal, this is indicated by "RSY". Test mode 1 Single alternating pulses are sent on the S/T-interface (2 kHz repetition rate) Test mode 2 Continuous alternating pulses are sent on the S/T-interface (96 kHz) Reset state A hardware or software reset (RES) forces the SBCX to an idle state where the analog components are disabled (transmission of INFO0) and the S/T line awake detector is inactive. Thus activation from the NT is not possible. Clocks are still supplied and the outputs are in a low impedance state. 4.3.2 State Machine LT-S Mode Section 4.3.2 is applicable for LT-S mode. Semiconductor Group 136 Technical Description 4.3.2.1 LT-S Mode State Diagram RST TIM RES DR * DC DI ARD1) ARD1) TIM DR DR TIM TMI 4) Reset i0 RES Any State G4 Pend. Deact. i0 i0 i0 or 32 ms DR Test Mode i it DC * TMI Any State Wait for DR i0 * DC DI DC DR ARD1) G1 Deactivated i0 i0 AR DC ARD i0 G2 Pend. Act. i2 i3 DR i3 or NT-STAR AI DC ARD 2) G3 Activated i4 i3 i3 DR OUT i3 IOM R IN DC RSY 3) ARD G2 Lost Framing i2 i3 Ind. Cmd. DR State S/T ix ir ITD04012 Notes: 1. ARD stands for AR or ARL 2. NT star: transition from `G2 pend. act.' to `G3 activated' takes place when the first branch of the star is synchronized 3. NT star: Transition from state `G3 activated' to `G2 Lost Framing' is disabled. 4. TMI = TM1 or TM2 Figure 68 State Transition Diagram in LT-S Mode Semiconductor Group 137 Technical Description 4.3.2.2 LT-S Mode Transition Criteria The transition criteria used by the SBCX are described in the following sections. They are grouped into: - C/I commands - Pin states - Events on the S/T-interface. 4.3.2.2.1 C/I Commands AR ARL DC DR RES TM1 Activation Request. This command is used to start an exchange initiated activation. Activation request loop. The SBCX is requested to operate an analog loop-back close to the S/T-interface. Deactivation Confirmation. Transfers the LT-S into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Deactivation Request. Initiates a complete deactivation from the exchange side by transmitting INFO 0. Unconditional command. Please refer to section 4.3.1.2.1 for details. Test Mode 1. Transmission of single pulses on the S/T-interface. The pulses are transmitted with alternating polarity at a frequency of 2 kHz. TM1 is a unconditional command. Test Mode 2. Transmission of continuous pulses on the S/T-interface. The pulses are sent with alternating polarity at a rate of 96 kHz. TM2 is a unconditional command. TM2 4.3.2.2.2 Pin States Pin-RES Pin Reset. Please refer to section 4.3.1.2.2 Pin-NT-STAR Device operates in NT-STAR mode. In this mode detection of INFO 3 is not essential in the state"G2 pend. act." for a transfer to "G3 activated". The transfer will be accomplished as soon as any one branch of the star is synchronized. NT-STAR set to LOW will disable the transition from "G3 activated" to "G2 Lost framing". Therefore, C/I indication "AI" will stay even when i3 is lost. 4.3.2.2.3 S/T-Interface Events I0 I0 I3 I3 INFO 0 detected Level detected (signal different to I0) INFO 3 detected Any INFO other than INFO 3 Semiconductor Group 138 Technical Description 4.3.2.3 Transmitted Signals and Indications in LT-S Mode The following signals and indications are issued on the IOM-2 and S/T-interface. 4.3.2.3.1 C/I Indications Abbreviation TIM RSY MAIC AR CVR Indication (upstream) LT-S mode Timing Resynchronizing MAI change Activate request Far-end-code-violation Remark Interim indication during deactivation procedure Receiver is not synchronous Pin MAIn has changed. MAI (3:0) pins summarized and monitored in one indication. INFO 0 received from terminal. Activation proceeds. After the receipt of at least one illegal code violation CVR is indicated six times. This function must be enabled by setting the RCVE-bit in the configuration register. Synchronous receiver, i.e. activation completed. Timer (32 ms) expired or INFO 0 received after deactivation request AI DI Activate indication Deactivate indication 4.3.2.3.2 S/T-Interface Signals I0 I2 I4 It INFO 0 INFO 2 INFO 4 Pseudo ternary pulses at 2-kHz frequency (TM1). Pseudo ternary pulses at 96-kHz frequency (TM2). Semiconductor Group 139 Technical Description 4.3.2.4 States LT-S Mode G1 deactivated The SBCX is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. G2 pending activation As a result of an INFO 0 detected on the S/T line or an ARD command, the SBCX begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise reception of INFO 3 is to be implemented in software. In case of an ARL command, loop 2 is closed. G3 activated Normal state where INFO 4 is transmitted to the S/T-interface. The SBCX remains in this state as long as neither a deactivation nor a test mode is requested, nor the receiver loses synchronism. When receiver synchronism is lost, INFO 2 is sent automatically. After reception of INFO 3, the transmitter keeps on sending INFO 4. G2 lost framing This state is reached when the SBCX has lost synchronism in the state G3 activated. G4 pending deactivation This state is triggered by a deactivation request DR. It is an unstable state: indication DI (state "G4 wait for DR.") is issued by the SBCX when: either INFO0 is received, or an internal timer of 32 ms expires. G4 wait for DR Final state after a deactivation request. The SBCX remains in this state until a response to DI (in other words DC) is issued. Test mode 1 Single alternating pulses are sent on the S/T-interface (2-kHz repetition rate). Test mode 2 Continuous alternating pulses are sent on the S/T-interface (96 kHz). 4.3.3 State Machine NT Mode Section 4.3.3 is applicable for NT mode. Semiconductor Group 140 Technical Description 4.3.3.1 NT Mode State Diagram RST TIM RES DR * DC DI ARD1) ARD1) TIM DR DR TIM TMI Reset i0 RES Any State G4 Pend. Deact. i0 i0 i0 or 32 ms DR Test Mode i it DC * TMI Any State G4 Wait for DR i0 * DC DI DC DR ARD1) G1 Deactivated i0 i0 i0 AR DC DR G1 i0 Detected i0 * ARD1) AR ARD G2 Pend. Act. i2 i3 DR i3 or NT_STAR AID RSY ARD G2 Lost Framing S/T i2 RSY DR i3 AID ARD1), AID 2) 2) 3) OUT IN i3 & ARD1) RSY i3 AI ARD DR IOM R Ind. Cmd. G2 Wait for AID 4) i2 i3 State S/T ix ir ARD 1) AI i3 & AID 2) RSY i4 i3 ITD04013 RSY RSY G3 Lost Framing U i2 * AID DR G3 Activated 4) Notes: 1. ARD = AR or ARL 2. AID = AI or AIL 3. Transition takes place as soon as one branch of the star has detected INFO 3. 4. With NT-STAR selected transfer to "G2 lost framing" state is not possible. Figure 69 NT Mode State Diagram Semiconductor Group 141 Technical Description 4.3.3.2 NT Mode Transition Criteria The transition criteria used by the SBCX are described in the following sections. They are grouped into: - C/I commands - Pin states - Events or the S/T-interface. 4.3.3.2.1 C/I Commands AR ARL AI AIL DC DR RES RSY TM1 Activation Request. This command is used to start an exchange initiated activation. Activation request loop. The SBCX is requested to operate an analog loop-back close to the S/T-interface. Activation Indication. Confirms that the U-interface is fully transparent, on D-channel data transfer is allowed. Activation Indication loop. Deactivation Confirmation. Transfers the NT into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Deactivation Request. Initiates a complete deactivation from the exchange side by transmitting INFO 0. Unconditional command. Please refer to section 4.3.1.2.1 for details. Resynchronizing. The U-interface has not obtained or lost synchronization. INFO 2 is transmitted consequently by the SBCX. Test Mode 1. Transmission of single pulses on the S/T-interface. The pulses are transmitted with alternating polarity at a frequency of 2 kHz. TM1 is an unconditional command. Test Mode 2. Transmission of continuous pulses on the S/T-interface. The pulses are sent with alternating polarity at a rate of 96 kHz. TM2 is an unconditional command. TM2 Semiconductor Group 142 Technical Description 4.3.3.2.2 Pin States Pin-RES Pin Reset. Please refer to section 4.3.1.2.2 for details. Pin-NT-STAR Device operates in NT-STAR mode. In this mode detection of INFO 3 is not essential for a transfer to "G2 wait for AI". The transfer will be accomplished as soon as any one branch of the star is synchronized. A transfer from states "G2 wait for AI" and "G3 activated" to state "G2 lost framing" is not possible with NT-STAR pin set to low. Pin-TM1 Pin-TM2 Transfers the SBCX into the "Test mode i" state. Here a 2-kHz signal of alternating pulses is transmitted on the S/T-interface. Transfers the SBCX into "Test Mode i" state. Here a signal consisting of continuous binary ZEROs is sent at the rate of 96 kHz. 4.3.3.2.3 S/T-Interface Events I0 I0 I3 I3 4.3.3.3 INFO 0 detected Level detected (any signal different to I0) INFO 3 detected Any INFO other than INFO 3. Transmitted Signals and Indications in NT Mode The following signals and indications are issued on the IOM-2 and S/T-interface. 4.3.3.3.1 C/I Indications Abbreviation TIM RSY MAIC AR CVR Indication (upstream) NT Mode Timing Resynchronizing MAI change Activate request Far-end-code-violation Remark S transceiver requires clock pulses Receiver is not synchronous Pin MAIn has changed INFO 0 received After each multi-frame the receipt of at least one illegal code violation is indicated six times. This function must be enabled by setting the RCVE-bit in the configuration register. Synchronous receiver Timer (32 ms) expired or INFO 0 received after deactivation request AI DI Activate indication Deactivate indication Semiconductor Group 143 Technical Description 4.3.3.3.2 S/T-Interface Signals I0 I2 I4 It INFO 0 INFO 2 INFO 4 Pseudo ternary pulses at 2-kHz frequency (TM1). Pseudo ternary pulses at 96-kHz frequency (TM2). States NT Mode 4.3.3.4 G1 Deactivated The SBCX is not transmitting. No signal is detected on the S/T-interface, and no activation command is received in C/I channel. DI is output in the normal deactivated state, and TIM is output as a first step when an activation is requested from the S/T-interface. G1 I0 Detected An INFO 0 is detected on the S/T-interface, translated to an "Activation Request" indication in the C/I channel. The SBCX is waiting for an AR command, which normally indicates that the transmission line upstream (usually a two-wire U interface) is synchronized. G2 Pending Activation As a result of the ARD command, and INFO 2 is sent on the S/T-interface. INFO 3 is not yet received. In case of ARL command, loop 2 is closed. G2 wait for AID INFO 3 was received, INFO 2 continues to be transmitted while the SBCX waits for a "switchthrough" command AID from the device upstream. G3 Activated INFO 4 is sent on the S/T-interface as a result of the "switch through" command AID: the B and D-channels are transparent. On the command AIL, loop 2 is closed. G2 Lost Framing S/T This state is reached when the SBCX has lost synchronism in the state G3 activated. G3 Lost Framing U On receiving an RSY command which usually indicates that synchronization has been lost on the two-wire U interface, the SBCX transmits INFO 2. Semiconductor Group 144 Technical Description G4 Pend. Deact. This state is triggered by a deactivation request DR, and is an unstable state. Indication DI (state "G4 wait for DR") is issued by the SBCX when: either INFO0 is received or an internal timer of 32 ms expires. G4 wait for DR Final state after a deactivation request. The SBCX remains in this state until an "acknowledgment" to DI (DC) is issued. Test Mode 1 Single alternating pulses are sent on the S/T-interface (2-kHz repetition rate). Test Mode 2 Continuous alternating pulses are sent on the S/T-interface (96 kHz). Semiconductor Group 145 Technical Description 4.4 4.4.1 Reset C/I Command RES Reset of the layer-1 state machine. SBCX is transmitting info 0 and does not react on received infos. RES is an unconditional command. 4.4.2 Hardware Reset RST All SBCX registers are set back to their initial values. At power up a reset pulse (RST = low active) of minimum 1 s should be applied to bring SBCX to the state "reset" in the L1 state machine. After that the SBCX may be operated according to the state diagrams. In NT mode the DCL is needed during the hardware reset for initialization. The devices fitting to the SBCX in NT mode (i.e. IECs and IBC) deliver the necessary clocks automatically. All MAI pins are tristate during RST = 0 or when the SBCX is in the state `reset', unless MAIM is programmed to 1. After reset MAI (3:0) are operated as input pins and MAI (7:4) as output pins (push/pull). The value after reset is 0. IDP0 and IDPI are tristate during RST = `0'. 4.4.3 Push/Pull Sensing After the hardware reset the SBCX senses in the monitor channel timeslot during the first two IOM frames, whether an external pull-up resistor is connected or not to pin IDP0. During this time of sensing it is necessary, that no other device connected to IDP0 sends informations in the monitor channel. As a result of the sensing procedure the pins IDP0, IDP1, X3 (if CEB) and MAI5 (if S/G) are either open drain outputs and therefore require the same pull-up resistor as pin IDP0 or push/pull outputs. Please note that the IOM-2 Interface Specification describes open drain data lines (IDP0 and IDP1) with external pull-up resistors. However, if operation is logical point-to-point, tristate operation is possible as well for the data lines. 4.4.4 Initializing LT-T Mode If the `Mode' pin is pin strapped to 1, after Hw-Reset the SBCX will start in LT-S mode. Until the SBCX is switched to LT-T mode by register setting, it may react to incoming signals on S0. Therefore the following sequence should be used: Hw-Reset Sw-Reset (write command `RES' to C/I) release Hw-Reset program Configuration Register: MODE to 1 for LT-T Mode write command `TIM' to C/I Semiconductor Group 146 Technical Description 4.5 Maintenance Functions The technical description of maintenance functions follows in the next sections. The sections "Test Modes" and "System Measurement" of chapter 3 have not been included as they contain primarily application information. 4.5.1 4.5.1.1 Function The analog loop may be closed in three different locations: in the NT1 (No. 2), the NT2 (No. 3) and the terminal or PBX (No. A). The loop is closed close to the S/T-interface. No external S/T-interface circuitry is required to close these loop-backs. Initialization Two alternatives are provided to close the complete loop-back. The first method makes use of the C/I command ARL. In TE and LT-T modes "ARL" is regarded as an unconditional command. It may therefore be issued independently of the current operational state. In NT and LT-S modes the "ARL" command is recognized in the states: - - - - G4 pending deactivation G4 wait for DR G1 deactivated G1 I0 detected (NT only) Test Loop-Backs Complete Loop-Backs (No. 2, No. 3, and No. A) The command "ARL" has to be applied continuously while the loop-back is required. The second alternative to close the analog loop-back is to set the "SC" bit in the loop-back register. This option is only available in LT-S and NT mode when the device is fully activated (C/I = AI). Transparency The user may choose whether the complete loop-back data is to be put transparently onto the S/T-interface or not. The selection is performed with the "LP" bit in the configuration register. Semiconductor Group 147 Technical Description 4.5.1.2 Function Single Channel Loop-Backs (No. 4, No. B2, No. C) Partial loop-backs may be closed on the IOM-2 or the S/T-interface. Loop-backs No. B 2 (NT2), No. C (NT1) and No. 4 (terminal and PBX) are closed on IOM-2 and loop-back the data from the S/T-interface. Initialization Partial loop-backs are entirely controlled by the loop-back register. Loop-backs are available for both B channels on the S/T and IOM-2 interface. By setting the corresponding bit in the loop-back register to ONE a loop-back is closed. IOM-2 loopbacks (IB1, IB2) may be closed in combination, i.e. IB1 = ONE and IB2 = ONE will close loop-backs for both B channels. Additionally the command IB12 allows to interchange the B1 and B2 channel. IB12 only works in conjunction with IB1 and IB2. S/T loop backs (SB1, SB2) can be closed in LT-S and NT mode. Single channel loop-backs can only be closed in the fully activated state. Transparency All single channel loop-backs are transparent. 4.5.2 Function Any illegal code violations on the S/T bus result in the C/I Code "CVR" to be issued in 6 successive IOM-2 frames. This function is implemented according to ANSI T1.605. It is independent of multiframing. Initialization The detection of illegal code violations is enabled by setting bit "RCVE" in the configuration register to ONE. Monitoring of Illegal Code Violations Semiconductor Group 148 Technical Description 4.6 Clock Generation and Clock Characteristics This section deals with clock generation requirements for slave and master modes and the characteristics of clock signals produced by the SBCX. The following requirements apply to all operational SBCX modes: Clock Requirements Master clock nominal frequency: Master clock overall tolerance: Master clock duty cycle: 7.68 MHz 100 ppm see figure 70 The inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". The timing measurements are made at 3.5 V for a logic "1" and 0.8 V for a logic "0". 3.5 V 0.8 V t WH tP t WL ITT00723 Figure 70 Dynamic Characteristics of Duty Cycle Table 25 Duty Ratio Pin XTAL1, XTAL2 Parameter High phase of crystal/clock Low phase of crystal/clock Period of crystal/clock Symbol min. Limit Values max. ns ns 130.34 ns 35 35 130.08 Unit tWH tWL tP Crystal specification and recommendations regarding the oscillator circuit are presented in section 4.7.2. Semiconductor Group 149 Technical Description Propagation Delay The delay from the IOM-2 to the S/T-interface and vice versa is independent of the direction. Table 26 Parameter min. Signal delay S IOM Signal delay IOM S 45 45 Limit Values typ. 65 65 max. 90 90 s s Unit Condition CL = 150 pF CL = 150 pF The requirements for input jitter and the operation of the implemented transmit and receive PLLs are dependent on the operational SBCX modes. Details on these themes are described in the following sections. 4.6.1 4.6.1.1 NT and LT-S Mode Transmit and Receive PLL The transmit PLL (XPLL) synchronizes a 192 kHz transmit bit clock to the IOM-2 clock FSC (8 kHz) derived from the oscillator clock. When the oscillator clock is synchronous to FSC (fixed divider ratio of 960) the XPLL will not perform any tracking after having locked the phase, i.e. the input jitter on clocks XTAL and FSC will not be increased. Alternatively, when a free running oscillator is used, XPLL tracking increases FSC jitter by 130 ns. This reduces the allowable input jitter of FSC to less than 130 ns peak-to-peak (see also following section "jitter"). - In a point-to-point or extended bus configuration the Receive PLL (RPLL) recovers bit timing from the detectors output signal and provides a synchronous 1536-kHz clock (adaptive timing recovery from the receive data stream on the S-interface). Divided by eight this clock is used as 192-kHz receive data clock (PP). - In a passive bus configuration, a 192-kHz receive clock (MP) generated by the transmit PLL (XPLL) is used to sample the input data (fixed timing recovery). Semiconductor Group 150 Technical Description XPLL MP FSC DCL RPLL PP ITS03999 Figure 71 Clock System of the SBCX in NT and LT-S Mode 4.6.1.2 Jitter Requirements According to ITU I.430 the maximum jitter in an NT output sequence is 5 % of a bit period (260 ns). Two cases need to be distinguished for SBCX input jitter requirements: q Crystal as clock source With a crystal as clock source the PLL works permanently to synchronize the master clock on to the FSC reference signal. Each tracking step produces 65 ns jitter so that a total of 130 ns "selfinitiated" jitter results under ideal circumstances. To be below the specified limit the FSC input jitter should not exceed 100 ns (30 ns margin) in this configuration. q Synchronized, external clock source In case an externally synchronized master clock is provided at pin XTAL1, the XPLL stops regulating once it has locked successfully. Therefore no "self-initiated" jitter is produced. All input jitter (FSC and master clock) is passed on transparently to the S/T-interface. The super imposed jitter of FSC and master clock may therefore not exceed 260 ns. Semiconductor Group 151 Technical Description 4.6.2 4.6.2.1 LT-T and TE Mode Receive PLL in TE and LT-T Mode The Receive PLL (RPLL) recovers bit timing from the detector's output signal and provides a synchronous 1536-kHz clock (adaptive timing recovery). Divided by eight this clock is used as 192-kHz receive data clock and as transmit data clock (PP). The receive PLL performs PLL tracking each 250 s after detecting the phase between the F/L transition of the receive signal and the covered clock. A phase adjustment is done by adding or subtracting 65 ns to or from a 1536-kHz clock cycle. The 1536-kHz clock is then used to generate any other clock synchronized to the line. PP RPLL DCL BCL FSC ITS04000 Figure 72 Receive PLL of the SBCX in TE Mode Slip Detector RPLL PP FSC DCL ITS04001 C REF Figure 73 Receive PLL of the SBCX in LT-T Mode Semiconductor Group 152 Technical Description 4.7 4.7.1 Elastic Buffers in LT-T Mode Elastic Buffer In LT-T mode the SBCX provides a buffer designed as a wander-tolerant system. This is required because the SBCX is a slave to both interfaces and the data clocks of the two interfaces have a time dependent phase relationship. The SBCX enables intermediate storage of 3 x B1 octets, 3 x B2 octets and 6 D-bits for phase difference and wander absorption. The elastic buffer of the SBCX compensates a maximum phase wander of 50 s peak-to-peak and a slip detector indicates when this limit is exceeded. Setting the C/W/P-bit in the configuration register gives a warning when a slip of 25 s is exceeded. An indication (Slip detected) is released in the C/I channel. Note that the C/I is only a warning, data has not been lost at this stage. 4.7.1.1 Jitter Requirements In TE and LT-T mode ITU I.430 specifies a maximum jitter in transmit direction of - 7 % to + 7 %. Because the zero reference is difficult to determine 14 % of bit period (peak to peak) are accepted (i.e. 730 ns). This specification will be met by the SBCX provided that the master clock source is accurate within 100 ppm (dependent of crystal or external source). 4.7.1.2 Output Clock Characteristics In TE and LT-T mode various clock signals are supplied by the SBCX to facilitate system design. The following two tables specify these clock signals for TE and LT-T Mode. Table 27 Clock Characteristics TE Mode Pin DCL Parameter Output: 1536 kHz Output: 1536 kHz Output: 1536 kHz X3 Output: 768 kHz Output: 768 kHz Output: 768 kHz X0 and C/W/Pbit = 0 Output: 32 kHz Output: 32 kHz Output: 32 kHz Symbol min. Limit Values typ. 651 325 325 1302 651 651 31.25 15.6 15.6 max. 782 475 350 1450 782 782 31.4 15.8 15.8 ns ns ns ns ns ns s s s osc 100 ppm osc 100 ppm osc 100 ppm osc 100 ppm osc 100 ppm osc 100 ppm osc 100 ppm osc 100 ppm osc 100 ppm 520 175 300 1150 520 520 31.1 15.4 15.4 Unit Condition tP tWH tWL tP tWH tWL tP tWH tWL Semiconductor Group 153 Technical Description Table 27 Clock Characteristics TE Mode (cont'd) Pin X0 and C/W/Pbit = `1' Parameter Output: 16 kHz Output: 16 kHz Output: 16 kHz Symbol min. Limit Values typ. 62.5 31.25 31.25 max. 62.7 31.4 31.4 s s s osc 100 ppm osc 100 ppm osc 100 ppm 62.3 31.1 31.1 Unit Condition tP tWH tWL Duty Ratios Table 28 TE Clock Signals (IOM(R)-2 mode) Application TE DCL o:1536 kHz1) 1:1 FSC o:8 kHz1) 1:2 X3 o:768 kHz1) 1:1 The 1536-kHz clock is phase-locked to the receive S signal and derived using the internal DPLL and the 7.68 MHz 100 ppm crystal. A phase tracking with respect to "S" is performed once in 250 s. As a consequence of this DPLL tracking, the "high" state of the 1536-kHz clock may be either reduced or extended by one half 7.68-MHz period once every 250 s. Since the other signals are derived from this clock, the "high" or "low" states may likewise be reduced or extended by the same amount once every 250 s. 7.68 MHz 1536 kHz * * Synchronous to receive S/T. Duty Ratio 3 : 2 Normally 768 kHz ITD05427 Figure 74 Phase Relationships of TE Clock Signals Note: 1.536 and 768 kHz may also start with falling edge of 7.68 MHz clock due to the phase tracking mentioned above. 1) Synchronous to receive "S" line Semiconductor Group 154 Technical Description Table 29 Clock Characteristics LT-T Mode Pin X3 Parameter Output: 1536 kHz Output: 1536 kHz Output: 1536 kHz 4.7.2 Symbol min. Limit Values typ. 651 391 260 max. 716 476 281 ns ns ns osc 100 ppm osc 100 ppm osc 100 ppm 586 306 240 Unit Condition tP tWH tWL Recommended Oscillator Circuit In all applications the user has the choice to supply the master clock by crystal or by an external source. In case a crystal (serial resonance) is connected it should meet the following requirements: Nominal frequency 7.68 MHz 20 pF 0.5 pF 60 7 pF 50 pF Overall tolerance (crystal, capacitance...) 100 ppm Load capacitance Resonance resistance Shunt capacitance External load capacitance CL 33 pF 19 XTAL1 CL 7.68 MHz 33 pF 18 External Oscillator Signal 19 XTAL1 XTAL 2 N.C. 18 XTAL 2 CL Crystal Oscillator Mode Driving from External Source ITS00764 Figure 75 Recommended Oscillator Circuits Semiconductor Group 155 Technical Description 4.8 Analog Line Port The analog part of the SBCX consists of two major building blocks: - Receiver - Transmitter In addition external circuitry is required to connect both transmitter and receiver to the S/T-interface. The following three sections describe these functional blocks in detail. 4.8.1 Receiver Characteristics The receiver consists of a differential to single ended input stage, a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators. The following figure describes the functional blocks of the receiver. 50 k 40 k 40 k SR 1 SR 2 50 k Figure 76 Receiver Circuit The input stage works together with external 10 k resistors to match the input voltage to the internal thresholds. The data detection thresholds are chosen to 35 % of the peak voltage to increase the performance in extended passive bus configurations. However they never go below 85 mV with respect to the line signal level. This guarantees a maximum line attenuation of at least 13 dB in point-to-point configurations with a margin of more than 70 mVpp with respect to the specified 100 mVpp noise. Semiconductor Group + - Level Detect VREF1 2.5 V Peak Detector Data High VREF2 Data Low ITS03994 156 Technical Description Figure 77 Receiver Thresholds The peak detector requires maximum 2 s to reach the peak value while storing the peak level for at least 250 s (RC > 1 ms). The additional level detector for power up/down control works with fixed thresholds at 100 mV. The level detector monitors the line input signals to detect whether an INFO is present. In TE and LT-T mode, when closing an analog loop, it is therefore possible to indicate an incoming signal during activated loop. In NT and LT-S analog loop-back mode the level detector monitors its own loop signal and an incoming signal is not recognized. Semiconductor Group 157 Technical Description 4.8.2 Transmitter Characteristics The transmitter stage consists of two identical current limited voltage sources, one for each polarity of output pulses. The voltage source guarantees the required output voltages on 50 and 400 loads whereas the 5.6 load is current limited to maximum 13.4 mA. The opposite pin is always switched to ground. The rising and falling edges of the pulses on the 50 load is typically 300 ns. The following figure illustrates the transmitter stage. SX 1 VSEN 1 SON 2 SX 2 VSEN 2 SON 1 ITS03997 Figure 78 Transmitter Output Stage The dynamic transmitter characteristics are given by the control signals VSEN1,2 and SON1,2 delivered to the output stage. Both the switch and the voltage source enable signals are simple binary signals with slightly different timing according to the following figure. Active VSEN 1(2) Active 5.2 s Active SON1(2) Active ITD03998 260 ns Figure 79 Dynamic Transmitter Characteristics Semiconductor Group 158 + + - VREF VREF Technical Description 4.8.3 S/T-Interface Circuitry In order to comply to the physical requirements of ITU recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the SBCX needs some additional circuitry. The transmitter of the SBCX is identical to that of both PEB 2080 S-Bus Interface Circuit (SBC) and PEB 2086 ISDN Subscriber Access Controller (ISAC(R)-S), hence the line interface circuitry should be the same. The external resistors (20 ... 40 ) are required in order to adjust the output voltage to the pulse mask (nominal 750 mV according to ITU I.430, to be tested with the command "TM1") on the one hand and in order to meet the output impedance of minimum 20 (transmission of a binary zero according to ITU I.430, to be tested with the command "TM2") on the other hand. 20...40 SX1 2,0...2,4 V SBCX 2:1 VDD 20...40 GND Overvoltage Protection S-Bus Connector SX2 DC Point ITS03732 Figure 80 External Circuitry Transmitter Semiconductor Group 159 Technical Description The receiver of the SBCX is symmetrical. 10 k overall resistance are recommended in each receive path. Although it is possible to place two single 10 k resistors either between transformer and diode circuit or between chip and diode circuit it is preferable to split the resistance into two resistors for each line. This allows to place a high resistance between the transformer and the diode protection circuit (required to pass 96 kHz input impedance test of ITU I.430). The remaining resistance (2 k) protects the SBCX itself from input current peaks. The following figure illustrates this recommendation. 2 k SX1 8 k 2:1 SBCX 2 k SX2 VDD GND 8 k Overvoltage Protection S-Interface Connector DC Point ITS03733 Figure 81 External Circuitry Receiver Semiconductor Group 160 Technical Description 4.8.3.1 S/T-Interface Transformer The SBCX is connected to the S/T-interface by the use of a 2:1 transformer for the receiver and the transmitter respectively. The line side of the transformer should be centre tapped for the phantom power supply. The model parameters of the transformer are defined below (all measurements at 10 kHz): primary to secondary transformer ratio: primary total DC resistance: primary inductance: primary inductance with secondary short circuited: primary capacitance with secondary open: 1:2 1 % R 10 LM > 20 mH LP < 20 H C < 40 pF 2:1 LP R C LM Linie Side Ideal Transformer ITS04021 Figure 82 Transformer Model Semiconductor Group 161 Technical Description 4.8.3.2 Line Overload Protection (Transmitter, Receiver) In order to protect the SBCX from over-current pins SX1, SX2 and SR1, SR2 are equipped with internal protection circuits. The following figures indicate what limits may not be exceeded to avoid permanent damage to the analog port. These figures may be used to deduct requirements for external over voltage protection. The maximum input current (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse as outlined in the following figure. Device under test t t WI Condition: All other pins grounded ITS04532 Figure 83 Test Condition for Maximum Input Current Semiconductor Group 162 Technical Description 4.8.4 Transmitter Input Current The destruction limits for negative input signals (Ri 2 ) and for positive input signals (Ri 200 ) are given in the following figure. A 50 5 0.5 0.05 t w1 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 1s ITD02340 Figure 84 Destruction Limits Transmitter Input Current Semiconductor Group 163 Technical Description 4.8.5 Receiver Input Current The destruction limits (Ri 300 ) are given in the following figure. A 5 1 0.1 0.01 0.005 t w1 10 -10 10 -4 10 -1 1s ITD02338 Figure 85 Destruction Limits Receiver Input Current Semiconductor Group 164 Electrical Characteristics 5 Electrical Characteristics All characteristics given are valid under the following conditions unless otherwise indicated: TA = - 20 to 70 C; VDD = 5 V 5 %; VSS = 0 V 5.1 Absolute Maximum Ratings - 20 to 70 C - 65 to 125 C - 0.4 to VDD + 0.4 V 1W Ambient temperature under bias Storage temperature Voltage on any pin with respect to ground Power dissipation Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Contact Resistance Silicon-Case RTHK P-DIP-28 P-LCC-28-R 29.6 K/W 11.5 K/W Silicon-Environment RTHU 49 K/W 60 K/W Semiconductor Group 165 Electrical Characteristics 5.2 Power Supply VDD = 5 V 0.25 V The analog receiver part has a power supply rejection of better than - 40 dB up to 100 kHz as shown in the following figure. However, due to the digital oversampling technique the overall receiver characteristics exceed the given value beyond 200 kHz. 0 dB ITD03996 -10 dB -20 dB -30 dB -40 dB -50 dB 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Figure 86 Power Supply Rejection SBCX Receiver 5.3 Capacitances TA = 25 C; VDD = 5 V 5 %; VSS = 0 V; fC = 1 MHz Pin All pins except SX1, 2 SX1, 2 XTAL1, 2 Parameter Pin capacitance Output capacitance against VSS External load capacitance Symbol min. Limit Values max. 7 10 50 pF pF pF Unit CIO COUT CL Semiconductor Group 166 Electrical Characteristics 5.4 Pin All pins except SX1, 2; SR1, 2; XTAL1, 2 IDP1, 0 All pins except SX1, 2; SR1, 2; XTAL1, 2 SX1, SX2 DC Characteristics Parameter Input low voltage Input high voltage Output low voltage Output low voltage Output high voltage Symbol Limit Values min. max. 0.8 V V V V V V 1 1 2.03 2.10 7.5 10 2.31 2.39 13.4 A A V V mA k - 0.4 2.0 Unit Test Condition VIL VIH VOL VOL1 VOH VDD + 0.4 0.45 0.45 IOL = 2 mA IOL = 7 mA IOH = - 400 A IOH = - 100 A 0 V VIN VDD 0 V VOUT VDD 2.4 VDD - 0.5 Input leakage current Output leakage current Absolute value of output pulse amplitude (VSX2 - VSX1) Transmitter output current ILI ILO VX RL = 50 1) RL = 400 1) RL = 5.6 1) inactive or during binary one (VDD = 0 ... 5 V) during binary zero RL = 50 SX1, SX2 SX1, SX2 IX Transmitter output impedance ZX 0 SR1, SR2 XTAL1 XTAL1 XTAL2 XTAL2 Receiver input impedance Input high voltage Input low voltage Output high voltage Output low voltage k ZR VIH VIL VOH VOL 10 100 3.5 - 0.4 4.5 0.4 VDD = 5 V VDD = 0 V VDD + 0.4 1.5 V V V V IOH = 5 A, C 50 pF IOH = 5 A, C 50 pF Note: 1) Due to the transformers, the load resistance as seen by the circuit is four times RL Semiconductor Group 167 Electrical Characteristics 5.5 Power Consumption Limit Values min. typ. max. 60 mW Power-up Comment Parameter 50 chip load, inputs at VSS/VDD, 50 % bin. ZEROs in B1 and B2 channel No output loads 0 chip load and INFO2 transmitted 4 mW 108 mW Power-down Worst-case Note: For power consumption under emergency conditions please refer to corresponding application note. Semiconductor Group 168 Package Outlines 6 Package Outlines P-DIP-28-3 (Plastic Dual In-Line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" Dimensions in mm Semiconductor Group 169 GPD05590 Package Outlines P-LCC-28-1 (Plastic Leaded Chip Carrier Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 170 Dimensions in mm GPL05018 7 Appendix Appendix The appendix comprises three sections: Appendix A contains a collection of Delta- and Errata Sheets published for the SBCX, PEB 2081. These allow the user to identify technical differences between the latest SBCX versions. Appendix B summarizes the requirements of external components and gives addresses of recommended suppliers. Appendix C is a Quick Reference Guide containing the most important information regarding the SBCX. Semiconductor Group 172 Appendix A 7.1 Delta and Errata Sheets S/T Bus Interface Circuit Extended (SBCX) PEB 2081 Delta Sheet CMOS Differences between PEB 2081 Version 3.4 and Version 3.3 1. Programming the IOM(R)-2 channel register (address: 3H) with the value xxxx x1xx (DH = 1) in the LT-T mode has no influence on the indication. The indication in the state "activated" is always 1100 (AI). 2. Enabling the far-end-code violation function (FECV) according to ANSI T1.605 (RCVE = 1 in configuration register; address = 1H) the detection of at least one code violation within multiframe is indicated by the occurrence of six times the CI code 1011 (CVR). Semiconductor Group 174 S/T Bus Interface Circuit Extended (SBCX) PEB 2081 Errata Sheet for the Version 3.3 CMOS 1. Activation Indication After programming the IOM-2 Channel Register (address: 3 H) with the value xxxx x1xx (DH = 1) in the LT-T Mode, the indication of the state "activated" may be 0100 (RSY) instead of 1100 (AI). Although the indication is wrong the device works correctly. 2. Illegal Code Violation Indication After enabling the far-end code violation function (FECV) according to ANSI T1.605 (RCVE = 1 in configuration register; address: 1H) the device indicates illegal code violation in the CI channel: 1011 (CVR). The indication, once occurred, will only disappear when leaving the activated state. This function should not be programmed if using the versions 3.2 and 3.3. Semiconductor Group 175 S/T Bus Interface Circuit Extended (SBCX) PEB 2081 Errata Sheet for the Version 3.4 CMOS 1. Statemachine Toggling Receiving INFOX in TE or LT-T mode the statemachine may toggle betweenstateF5/F8 and state F6 or between state F5/F8 and state F7. While toggling the device stays in F6 or F7 for one IOM frame only. 2. NT Star Operation D-Channel handling in a star configuration (several SBCX in NT/LT-S mode, tied together at CEB and IOM) doesn't work properly. Corrupted D-channel data may be sent in DU direction on IOM. Semiconductor Group 176 05.96 Appendix B 7.2 External Components Information Appendix Transformers and Crystals Vendor List Transformers: Crystals: Frischer Electronic Schleifmuhlstrae 2 D-91054 Erlangen, Germany Advanced Power Components (APC) 47 Riverside Medway City Estate Strood County of Kent, GB Tel.: (044) 634-290 588 KVG Waibstadter Strae 2-4 D-74924 Neckarbischofsheim 2, Germany Tel.: (...7263) 648-0 NDK 2-21-1 Chome Nishihara Shibuya-Ku Tokyo 151, Japan Tel.: (03)-460-2111 or Cupertino, CA, USA Tel.: (408) 255-0831 Pulse Engineering P.O. Box 12235 San Diego, CA 92112, USA Tel.: (619) 268-2454 or 4, avenue du Quebec F-91940 Les Ulis, France or Dunmore Road Tuam County Galway, Ireland Tel.: (093) 24107 Saronix 4010 Transport at San Antonio Palo Alto, CA 94303, USA Tel.: (415) 856-6900 or via Arthur Behrens KG Schrammelweg 3 D-82544 Egling-Neufahrn, Germany S+M Components Balanstrae 73 P.O. Box 801709 D-81617 Munich, Germany Tel.: (...89) 4144-8041 Fax.: (...89) 4144-8483 Siemens Oostcamp Belgium Tele Quarz Landstrae 13 D-74924 Neckarbischofsheim 2, Germany Schott Corporation Suite 108 1838 Elm Hill Pike, Nashville, TN 37210, USA Tel.: (615) 889-8800 TDK Christinenstrae 25 D-40880 Ratingen 1, Germany Tel.: (...2192) 487-0 Semiconductor Group 178 Appendix Universal Microelectronics Vacuumschmelze (VAC) Gruner Weg 37 Postfach 2253 D-63412 Hanau 1, Germany Tel.: (...6181) 380 or 186 Wood Avenue South Iselin, NJ OB830, USA Tel.: (908) 603 5905 Valor Steinstrae 68 D-81667 Munchen, Germany Tel.: (...89) 480 2823 Fax.: (...89) 484 743 Vogt electronic AG Postfach 1001 D-94128 Obernzell, Germany Tel.: (...8591) 17-0 Fax.: (...8591) 17-240 Semiconductor Group 179 Appendix List of Transformer Manufacturers and S0 Transformers The following list contains transformers recommended by different manufacturers for use with Siemens S0 transceivers. Transformers marked with 1) have been tested in Siemens S evaluation boards and have shown positive test results concerning pulse shape and impedance requirements of ETS 300 012. This list is not completed, there may be other manufacturers as well as more types fitting to the SBCX. Manufacturers APC APC 2040 S APC 1020 S APC 3060 S APC 9018 D APC 3366 D Pulse Engineering PE-689751) PE-64995 PE-65495 PE-65795 PE-68995 S + M Components B78384-A1060-A21) B78384-P1111-A2 Vacuumschmelze VAC T60403-L4025-X0211) T60403-L4097-X0111) T60403-L5051-X0061) T60403-L4021-X066 T60403-L4025-X095 T60403-L4097-X029 T60403-L5032-X002 VALOR PT 5001 PT 5069 ST 5069 VOGT 543 21 002 001) 543 21 004 001) Transformers Semiconductor Group 180 Appendix C 7.3 Quick Reference Guide Quick Reference Guide Modes of Operation Configuration LT-S Point-Point/Bus NT Point-Point/Bus LT-T TE Pin Mode X0 X1 X2 X3 MAI0 MAI1 MAI2 MAI3 MAI4 MAI5 MAI6 MAI7 FSC DCL i: input o: output Note: 1) Choice for bus configuration (1 = bus). In LT-S mode only programmable. In NT mode programmable or pin strapping. Pin strapping has the higher priority. 2) CON-pin functionality is enabled if DH = "1" in the IOM-2 Channel register in LT-T mode. 3) CON-pin functionality is enabled if DH = "0" in the IOM-2 Channel register in TE mode. 1 i:TS0 i:TS1 i:TS2 i/o:CEB i:NT-STAR i:MPR1 i:MPR2 i:MPR3 o:MPR4 o:MPR5 o:MPR6 o:MPR7 i:8kHz i:512-8192kHz 0 i:0/i:1 1) i:0 i:1 i/o:CEB i:NT-STAR i:MFD i:TM1 i:TM2 o:MPR4 o:MPR5 o:MPR6 o:MPR7 i:8kHz i:512-8192kHz 1 i:TS0 i:TS1 i:TS2 o:1536kHz (3:2) i:MPR0 i:CON2) i:MPR2 i:MPR3 o:MPR4 o:S/G o:MPR6 o:MPR7 i:8kHz i:512-8192kHz 0 o:32/16kHz (1:1) i:0 i:0 o:768kHz (1:1) i:MPR0 i:CON3) i:MPR2 i:MPR3 o:MPR4 o:S/G if SGE = 1 o:MPR6 o:MPR7 o:8kHz (1:2) i:1536kHz (1:1) (cont'd) i: 0 input fixed to VSS i: 1 input fixed to VDD Semiconductor Group 182 Quick Reference Guide Modes of Operation (cont'd) Configuration LT-S Point-Point/Bus NT Point-Point/Bus LT-T TE Register Configuration Bit 0 (Mode) [0] Configuration Bit 1 (C/W/P) [0] Configuration Bit 5 (FSMM) [0] Configuration Bit 6 (MAIM) [0] SM/CI Bit 0 (MIO) [0] SM/CI Bit 2 (SGE) [0] IOM-2 Channel Bit 2 (DH) [0] 0 0/11) 0/1 0 0 0 0/15) 0/17) 0/11) 0/1 0 0 0 0/15) 1 0/12) 0 0 0 0 0/16) 0/17) 0/13) 0 0 0 0/18) 0/17) Notes: 1) Choice for bus configuration (1 = bus). In LT-S Mode only programmable. In NT mode programmable or pin strapping. Pin strapping has the higher priority. 2) Slip warning control. C/W/P = 0 will issue C/I "Slip" code warning after 50 s wander. C/W/P = 1 will issue the "Slip" code warning after 25 s. 3) PCK (pin X0) frequency select. C/W/P = 0 will issue a power converter clock frequency of 32 kHz, C/W/P = 1 will issue 16 kHz. 4) Select "1" for intelligent NT applications to ensure partial TIC Bus evaluation (see section 3.3.5.5). 5) Select "1" for point-to-multipoint configurations to ensure D-channel collision resolution according to ITU I.430 (see section 2.1.7 and 3.3.5.4). 6) For normal D-channel collision procedure program DH = "0". 7) 0: MAI pins I/O specific; 1: MAI pins only I/O. 8) In TE Mode pin MAI5 outputs a D-channel enable signal, which may be used by a general purpose HDLC controller for LAP D handling. The signal contiuously monitors the D-E channel status and provides a stop/go information. [0] Initial register bit value after hard- or software reset. Semiconductor Group 183 Quick Reference Guide MON-8 Configuration Register - (Read/Write, Address: 1H) Format: Initial Value: 00H Bit-name MODE C/W/P Description Pin MODE = VDD (LT-S, LT-T): 0: LT-S mode selected 1: LT-T mode selected MFD MAIM FSMM LP SQM RCVE C/W/P MODE LT-S and NT mode: Configuration 0: point-to-point or extended passive bus configuration (adaptive timing recovery). In NT mode the pin X0 (= BUS) must be low. 1: short passive bus configuration (fixed timing recovery) in LT-T mode: Wander detection (warning in C/I, data may be lost!) 0: "SLIP" after 50 s wander 1: "SLIP" after 25 s wander in TE mode: Power converter clock frequency supplied at pin X0 0: 32 kHz 1: 16 kHz SQ channel handling mode selection 0: non-auto mode only S1 and Q channels 1: transparent mode S1, S2 and Q channels 0: 1: normal operation Far-end-code-violation (FECV) function according to ANSI T1.605 implemented. SQM RCVE LP NT/LT-S mode: 0: transparent analog loop 1: non-transparent analog loop TE / LT-T mode: 0: non-transparent analog loop 1: external transparent loop NT/LT-S mode: 0: normal operation 1: Finite state machine interchanged (LT-S NT) MAI pins mode: 0: I/O-specific or standard I/O MAI interface 1: P interface mode for MAI interface Multi-frame disable (write): 0: All multi-frame functions active. In NT mode the pin MAI1 (= MFD) must be low. 1: Multi-frame generation (NT, LT-S) or synchronization (TE, LT-T) prohibited. No SQ monitor messages released. Multi-frame detected (read): 0: No multi-frame synchronization achieved. 1: Multi-frame synchronization achieved. FSMM MAIM MFD Semiconductor Group 184 Quick Reference Guide MON-8 Loop-Back Register - (Read/Write, Address: 2H) Format: Initial value: 02H Bit-name AST Description ASynchronous Timing In NT and LT-S mode; only NT state machine 0: LT-S: command TIM in C/I NT: asynchronous wake up 1: LT-S: asynchronous wake up (useful for the Intelligent NT) NT: command TIM in C/I Loop-back B1 channel at S/T-interface in NT/LT-S mode Loop-back B2 channel at S/T-interface in NT/LT-S mode Loop-back complete (2B + D) at S/T-interface in NT/LT-S mode Loop-back B1 channel at IOM-2 interface Loop-back B2 channel at IOM-2 interface Loop-back B1 into B2 channel and vice versa at IOM-2 interface. Additionally IB1 and/or IB2 must be set. AST SB1 SB2 SC IB1 IB2 1 IB12 SB1 SB2 SC IB1 IB2 IB12 Semiconductor Group 185 Quick Reference Guide MON-8 IOM(R)-2-Channel Register - (Read/Write, Address: 3H) Format: Initial value: 00H B1L B1D B2L B2D DL DH CIL CIH Bit-name B1L Description B1 channel location 0: normal 1) 1: B1 channel in IOM-2 channel 0 B2 channel location 0: normal 1) 1: B2 channel in IOM-2 channel 0 D-channel location 0: normal 1) 1: D-channel in IOM-2 channel 0 CI channel location 0: normal 1) 1: in IOM-2 channel 0 B1 channel direction 0: normal (IDP0 is data output, IDP1 is data input) 1: IDP0 and IDP1 interchanged for B1 channel B2 channel direction 0: normal (IDP0 is data output, IDP1 is data input) 1: IDP0 and IDP1 interchanged for B2 channel D-channel handling 0: LT-S, LT-T and NT mode: transparent TE mode: Collision detection according to ITU I.430 1: NT and LT-S mode: D-channel access control TE mode: transparent D-channel LT-T mode: D-channel collision resolution according to ITU I.430 CI channel handling 0: normal C/I access in the pin strapped IOM-2 channel 1: disabled, access to C/I is only possible via the SM/CI register B2L DL CIL B1D B2D DH CIH Notes: 1) In LT-S and LT-T mode: pin strapped IOM-2 channel In NT and TE mode: IOM-2 channel 0 Semiconductor Group 186 Quick Reference Guide MON-8 SM/CI Register - (Read/Write, Address: 4H) Format: Initial value: CI, 0H Bit-name CI (3:0) Description CI channel When CIH-bit is set to one the commands are input in the monitor channel CI (3:0). The indication can always be read via monitor channel CI (3:0). Time-Out Disable 0: monitor timeout (minimum 5 ms) enabled 1: monitor timeout disabled Stop / Go Enable 0: normal 1: In TE mode pin MAI5 outputs S/G Maintenance Input Output (MAIM = 0) 0: I/O-specific functions on MAI interface 1: Standard I/O functions on MAI interface CI3 CI2 CI1 CI0 TOD SGE 0 MIO TOD SGE MIO Semiconductor Group 187 Quick Reference Guide MON-8 MAI Pin Register - (Read/Write, Address: 5H) Format: Initial value: 00H MPR7 MPR6 MPR5 MPR4 MPR3 MPR2 MPR1 MPR0 Bit-name MPR (7:0) Description access to MAI(7:0) pins if MAI interface in standard I/O or I/O specific function mode In case the P interface was selected as the MAI interface mode (MAIM = 1) the MAI pin register is defined as follows (only "write to register" operation will be accepted). Format: (write only) WR RD A1 A0 INT D2 D1 D0 Bit-name D0 ... D2 (MAI0:2) INT (MAI3) A0 ... A1 (MAI4:5) RD (MAI6) WR (MAI7) Description Data pin (input/output) Interrupt (input), Read request control: 0: Single Address read operation 1: Complete Address (0 ... 3) read operation Address pins (output) Read signal (output) 0: Read operation 1: Write operation (if WR = 0) Write Signal (output) 0: Write operation 1: Read operation (if RD = 0) Semiconductor Group 188 Quick Reference Guide TE/LT-T Modes State Diagram DC DI TIM DI TIM TMI TMI 5) Test Mode i it * F3 Power Down i0 ARp & CON i0 DI TIM ARp & CON DI i0 PU AR p 3) F4 Pend. Act. i1 i0 2) PU TIM DIS F3 Power Up i0 i0 i0 TMI Any State i0 RSY i4 X F5/8 Unsynchron i0 i1 i2 i0 X DI 2) 1) Reset/Loop TIM AR X 2) i2 & i4 RST Any State RES + ARL F6 Synchronized i3 i4 AI p 4) i2 i2 X 2) DI i2 & i4 i0 DR AR TIM F7 Activated i3 Slip SLIP i2 X 2) F3 Pend. Deact. i0 i0 i4 0.5 ms i2 & i4 TIM IN IOM R Ind. Cmd. F7 Slip Detected i3 i4 S/T ix State ir ITD04010 Notes: 1. See state diagram for unconditional transitions for details 2. x = TM1 or TM 2 or RES or ARL x = TM1 & TM2 & RES & ARL 3. ARP = AR8 or AR10 4. AIP = AI8 or AI10 5. TMI = TM1 or TM2 Figure 87 State Transition Diagram in TE/LT-T Modes Semiconductor Group 189 Quick Reference Guide LT-S Mode State Diagram RST TIM RES DR * DC DI ARD1) ARD1) TIM DR DR TIM TMI 4) Reset i0 RES Any State G4 Pend. Deact. i0 i0 i0 or 32 ms DR Test Mode i it DC * TMI Any State Wait for DR i0 * DC DI DC DR ARD1) G1 Deactivated i0 i0 AR DC ARD i0 G2 Pend. Act. i2 i3 DR i3 or NT-STAR AI DC ARD 2) G3 Activated i4 i3 i3 DR OUT i3 IOM R IN DC RSY 3) ARD G2 Lost Framing i2 i3 Ind. Cmd. DR State S/T ix ir ITD04012 Notes: 1. ARD stands for AR or ARL 2. NT star: transition from `G2 pend. act.' to `G3 activated' takes place when the first branch of the star is synchronized 3. NT star: transition from state `G3 activated' to `G2 Lost framing' is disabled. 4. TMI = TM1 or TM2 Figure 88 State Diagram of the LT-S Mode Semiconductor Group 190 Quick Reference Guide NT Mode State Diagram RST TIM RES DR * DC DI ARD1) ARD1) TIM DR DR TIM TMI Reset i0 RES Any State G4 Pend. Deact. i0 i0 i0 or 32 ms DR Test Mode i it DC * TMI Any State G4 Wait for DR i0 * DC DI DC DR ARD1) G1 Deactivated i0 i0 i0 AR DC DR G1 i0 Detected i0 * ARD1) AR ARD G2 Pend. Act. i2 i3 DR i3 or NT_STAR AID RSY ARD G2 Lost Framing S/T i2 RSY DR i3 AID ARD1), AID 2) 2) 3) OUT IN i3 & ARD1) RSY i3 AI ARD 4) IOM DR R Ind. Cmd. G2 Wait for AID i2 i3 State S/T ix ir ARD 1) AI i3 & AID 2) RSY i4 i3 ITD04013 RSY RSY G3 Lost Framing U i2 * AID DR G3 Activated 4) Notes: 1. ARD = AR or ARL 2. AID = AI or AIL 3. Transition takes place as soon as one branch of the star has detected INFO 4. With NT-STAR selected transfer to "G2 lost framing" state is not possible Figure 89 NT Mode State Diagram Semiconductor Group 191 Quick Reference Guide C/I Codes Code IN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DR RES TM1 TM2 - - - - AR - ARL - - - - DC LT-S OUT TIM - - - RSY MAIC - - AR - - CVR AI - - DI IN DR RES TM1 TM2 RSY - - - AR - ARL - AI - AIL DC NT OUT TIM - - - RSY MAIC - - AR - - CVR AI - - DI IN TIM RES TM1 TM2 - - - - AR8 AR10 ARL - - - - DI TE/LT-T OUT DR RES TM1 TM2 SLIP1) RSY MAIC/DIS - PU AR - ARL CVR AI8 AI10 AIL DC 1) In LT-T mode only Semiconductor Group 192 |
Price & Availability of PSB2186H
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |